• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.3
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• pp.296-303
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• 2004

Recently, the ultra light metal structure with periodic and three dimensional truss elements takes attention because of its multi-functionality and substantial heat resistance. However, the complicated fabrication process leading to high cost has been a major obstacle to wide applications. In this paper, a new idea to construct an ultra light structure with periodic, three dimensional truss using metal wires is presented. To prove the practical validity, a Kagome-like structure was fabricated from stamped wires and punched face sheets. It was assembled by soldering. Through three-point bending and compression tests, the strength was evaluated and compared with the theory.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.332-336
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• 2001

In this study, the reaction at UBM(Under Bump Metallurgy) and solder interface was investigated. The UBM employed in conventional optical packages, Au/Pt/Ti layer, were found to dissolve into molten Au-Sn eutectic solder during reflow soldering. Therefore, the reaction with different diffusion barrier layer such as Fe, Co, Ni were investigated to replace the conventional Pt layer. The reaction behavior was investigated by reflowing the solder on the pad of the metals defined by Cr layer for 1, 2, 3, 4, and 5 minutes at $330^{\circ}C$. Among the metals, Co was found to be most suitable for the diffusion barrier layer as the wettability with the solder was reasonable and the reaction rate of intermetallic formation at the interface is relatively slow.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.6
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• pp.549-554
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• 2003

The purpose of this paper is to investigate the solder properties by the change of P mass percentage. Tension test, wetting balance test, spread test, and analysis of intermetallic compound after isothermal aging of Sn-2.5Ag-0.7Cu-0.005P, Sn-2.5Ag-0.7Cu-0.01P, Sn-2.5Ag-0.7Cu-0.02P, Sn-0.7Cu-0.005P were performed. Adding P in the solder alloys resulted in improvement of tensile strength, reduction of intermetallic compound growth, reduction of oxidization in fusible solders under wave soldering. After comparing solder alloy containing P with tin-lead eutectic solder alloy, P contained solders alloys showed much better solder properties than eutectic solder alloy. Furthermore, this solder alloy presented remarkable properties than any other lead-free solder alloy.

• Proceedings of the Korean Society for Quality Management Conference
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• 2004.04a
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• pp.302-306
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• 2004

When we include environment side safety, environmental material's reliability technology and study for the application method, the evidence supporting the investment of R&D person and financial. Clearly, the most important task in electrical and electronics company's product soldering process the probability of heavy metals exclude is to identify the mechanisms by which they may take place. Therefore, this study emphasis on the application environmental material classification and reliability technology.

• Applied Microscopy
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• v.46 no.3
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• pp.167-169
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• 2016

Solder/electroless nickel immersion gold (ENIG) joint sample which is comprised of dissimilar materials with different mechanical properties has limited the level of success in preparing thin samples for transmission electron microscopy (TEM). This short technical note reports the operation parameters for ultramicrotomy of solder joint sample and TEM analysis results. The solder joint sample was successfully sliced to 50~70 nm thick lamellae at slicing speed of 0.8~1.2 mm/s using a boat-type $45^{\circ}$ diamond knife. Ultramicrotomy can be applied as a routine sample preparation technique for TEM analysis of solder joints.

• Journal of the Korean Society of Industry Convergence
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• v.2 no.2
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• pp.131-137
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• 1999

Package crack caused by the soldering process in the surface mounting plastic package is evaluated by applying the energy release rate criterion. The package crack formation depend on various parameters such as chip set, chip size, package thickness, package width, material properties and the moisture content etc. The effects of chip set and the other parameters were estimated during the analysis of package cracks which were located in the edge of the upper interface of the chip and the lower interlace of the die pad. From the results, it could be obtained that the more significant parameters to effect the chip set are chip width.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.218-221
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• 2007

The surface mounting technology of 0402 electric chip part is necessary to fabricate a high density and multi-functional module, but there is a limitation of the technology, like as a bridge and self-alignement. This work estimated SMT processing factors of 0402 chip. To obtain optimum SMT process, we evaluated effects of stencil thickness, shape of hole on printability and mountability. Printability shows best results under the thickness of $80{mu}m$ with circle hole shape and 90% square hole shape. In case of chip mounting process, chip mis-alignment and bridge was occurred rarely in same conditions. In more thin stencil thickness, $50{mu}m$, strength of 1005 chip parts was poor, because of amount of printed solder was insufficient.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.229-231
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• 2007

Recently, 3D-electronic packaging by TSV is in interest. TSV(Through Silicon Via) is a interconnection hole on Si-wafer filled with conducting metal such as Copper. In this research, chips with TSV are connected by electroplated Sn bump without PR. Then chips with TSV are put together and stacked by the methode of Reflow soldering. The stacking was successfully done and had no noticeable defects. By eliminating PR process, entire process can be reduced and makes it easier to apply on commercial production.

• Progress in Superconductivity and Cryogenics
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• v.4 no.2
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• pp.11-15
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• 2002

High speed probe for measurement of sin91e flux quantum circuits is comprised of coaxial cables and microstrip lines in order to carry high speed signals without loss. For the impedance matching between coaxial cable and microstrip line, we have determined the dimension of the microstrip line with 50${\Omega}$ impedance by simulation and then have investigated the effect of line width and cross-sectional shape of signal line, dielectric material, thickness of soldering lead at the coaxial-to-microstrip transition Point, and the an91c between dielectric material and end part of the signal line on the characteristics of signal transmission of the microstrip line. From the simulation, we have found that these all parameter's had influenced on the characteristic of signal transmission on the microstrip line and should be reflected in fabricating high speed probe, We have also determined the dimension of coplanar waveguide to fabricate testing sample for performance test of high speed probe.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1292-1298
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• 2003

In this paper, dc reactor lot the inductive high-Tc superconducting fault current limiter (SFCL) was optimally designed by finite element method(FEM). The Prototype high-Tc do reactor was manufactured and compared to the results of design. This dc reactor consists of 4∼stacked double pancake coils which are wounded with Bi-2223 wire coated with SUS315L. Kapton tape is used for the insulation of turn to turn and layer to layer. Each pancake is connected in series by soldering Finally, optimal design and manufacture method lot the dc reactor is suggested in this paper. Through the comparison of result of optimal design and experimental result of prototype high-Tc superconducting dc reactor, reliance on the design of the high-Tc dc reactor tot the 1.2 kV/80 A SFCL is proved.