• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.63-67
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• 2016

In this paper, we present an indirect method of elastic modulus measurement for various lamination layers formed on polymer-based compliant substrates. Although the elastic modulus of every component is crucial for mechanically reliable microelectronic devices, it is difficult to accurately measure the film properties because the lamination layers are hardly detached from the substrate. In order to resolve the problem, 3-point bending test is conducted with a film-substrate specimen and area transformation rule is applied to the cross-sectional area of the film region. With known substrate modulus, a modulus ratio between the film and the substrate is calculated using bending stiffness of the multilayered specimen obtained from the 3-point bending test. This method is verified using electroplated copper specimens with two types of film-substrate structure; double-sided film and single sided film. Also, common dielectric layers, prepreg (PPG) and dry film solder resist (DF SR), are measured with the double-sided specimen type. The results of copper (110.3 GPa), PPG (22.3 GPa), DF SR (5.0 GPa) were measured with high precision.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.43-50
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• 2014

By the trends of electronic package to be smaller, thinner and more integrative, the reliability of interconnection between Si chip and printed circuit board is required. This paper reports on a study of high speed shear energy of Sn-4.0wt%Ag-0.5wt%Cu (SAC405) solder joints with different the thicknesses of electroless Ni-P deposit. A high speed shear testing of solder joints was conducted to find a relationship between the thickness of Ni-P deposit and the brittle fracture in electroless Ni-P deposit/SAC405 solder. A focused ion beam (FIB) was used to polish the cross sections to reveal details of the microstructure of the fractured pad surface with and without $HNO_3$ vapor treatment. The high speed shear energy of SAC405 solder joint with $1{\mu}m$ Ni-P deposit was found to be lower without $HNO_3$ vapor, compared to those of over $3{\mu}m$ Ni-P deposit. This could be due to the edge of solder resist in $1{\mu}m$ Ni-P deposit, which provides a fracture location for the weakened shear energy of solder joints and brittle fracture in high speed shear test. With $HNO_3$ vapor, the brittle fracture mode in high speed shear test decreased with increasing the thickness of Ni-P deposit. Then the roughness (Ra) of Ni-P deposits decreased with increasing its thickness. Thus, this gives the evidence that the decrease in roughness of Ni-P deposit for Eelectroless Ni/ Electroless Pd/ Immersion Au (ENEPIG) surface play a critical role for improving the robustness of SAC405 solder joint.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.57-62
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• 2012

In this paper, numerical analysis by finite element method, parameter design by the Taguchi method and ANOVA method were used to analyze about effect of design deviations and thickness variations on warpage of FCCSP substrate. Based on the computed results, it was known that core material in substrate was the most determining deviation for reducing warpage. Solder resist, prepreg and circuit layer were insignificant effect on warpage relatively. But these results meant not thickness effect was little importance but mechanical properties of core material were very effective. Warpage decreased as Solder resist and circuit layer thickness decreased but effect of prepreg thickness was conversely. Also, these results showed substrate warpage would be increased to maximum 40% as thickness deviation combination. It meant warpage was affected by thickness tolerance under manufacturing process even if it were met quality requirements. Threfore, it was strongly recommended that substrate thickness deviation should be optimized and controlled precisely to reduce warpage in manufacturing process.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.188-190
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• 2004

As an effort to reduce cost and lead-time and to increase flexibility and responsiveness, manufacturers are using digital printing in numerous process steps. Typically, these processes require the precise dispensing of various fluids. Piezo ink jet printheads are proving to be reliable tools for depositing active materials such as light emitting polymers (LEP) for mobile phone displays and color filter inks for liquid crystal displays. Ink jets are also being used to provide uniform coatings of polyimide alignment layers and spacers for LCDs. Success with legend printing on PCBs using ink jets has encouraged the design of equipment for directly printing both etch resist and solder mask for PCBs. Development of printers for passive components such as capacitors and resistors is underway. This paper will present the attributes of an ink jet printhead designed to a precision deposition tool and discuss how it is being used to digitally print electronic and flat panel display components. Status of commercialization of digital printing will be discussed along with issues to be resolved before wide adoption takes place.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.421-421
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• 2008

Generally, the polymer thick-film resistors for embedded organic or hybrid substrate are patterned by screen printing so that the accuracy of resistor pattern is not good and the tolerance of resistance is too high(${\pm}$20~30%). To reform these demerits, a method using Fodel$^{(R)}$ technology, which is the patterning method using a photosensitive resin to be developable by aqueous alkali-solution as a base polymer for thick-film pastes, was recently incorporated for the patterning of thermosetting thick-film resistor paste. Alkali-solution developable photosensitive resin system has a merit that the precise patterns can be obtained by UV exposure and aqueous development, so the essential point is to get the composition similar to PSR(photo solder resist) used for PCB process. In present research, we made the photopatternable resistor pastes using 8 kinds of epoxy acrylates and a conductive carbonblack (CDX-7055 Ultra), evaluated their developing performance, and then measured the resistance after final curing. To become developable by alkali-solution, epoxy acrylate oligomers with carboxyl group were prepared. Test coupons were fabricated by patterning copper foil on FR-4 CCL board, plating Ni/Au on the patterned copper electrode, applying the resistor paste on the board, exposing the applied paste to UV through Cr mask with resistor patterns, developing the exposed paste with aqueous alkali-solution (1wt% $Na_2CO_3$), drying the patterned paste at $80^{\circ}C$ oven, and then curing it at $200^{\circ}C$ during 1 hour. As a result, some test compositions couldn't be developed according to the kind of oligomer and, in the developed compositions, the measured resistance showed different results depending on the paste compositions though they had the same amount of carbonblack.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.76-81
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• 2011

A new via cutting structure in 2-layer DRAM package substrate has been fabricated to lower its power distribution network(PDN) impedance. In new structure, part of the via is cut off vertically and its remaining part is designed to connect directly with the bonding pad on the package substrate. These via structure and substrate design not only provide high routing density but also improve the PDN impedance by shortening effectively the path from bonding pad to VSSQ plane. An additional process is not necessary to fabricate the via cutting structure because its structure is completed at the same time during a process of window area formation. Also, burr occurrence is minimized by filling the via-hole inside with a solder resist. 3-dimensional electromagnetic field simulation and S-parameter measurement are carried out in order to validate the effects of via cutting structure and VDDQ/VSSQ placement on the PDN impedance. New DRAM package substrate has a superior PDN impedance with a wide frequency range. This result shows that via cutting structure and power/ground placement are effective in reducing the PDN impedance.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.1
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• pp.21-26
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• 2013

This study presents new analysis method to predict bending behavior of packaging substrate structure by comparing finite element method simulation and measured curvature using 3D scanner. Packaging substrate is easily bent and deflected while undergoing various processes such as curing of prepreg and copper pattern plating. We prepare specimens with various conditions and measure contours of each specimen and compute the residual stresses on deposited films using analytical solution to find the principle of bending. Core and prepreg in packaging substrate are made up of resin and bundles of fiber which exist orthogonally each other. Anisotropic material properties cause peculiar bending behavior of packaging substrate. We simulate the bending deflection with finite element method and verify the simulated deflection with measured data. The plating stress of electrodeposited copper is about 58 MPa. The curing stresses of solder resist and prepreg are about 13 MPa and 6.4 MPa respectively in room temperature.

• Journal of Advanced Technology Convergence
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• v.2 no.4
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• pp.1-6
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• 2023

Research on power inductor surface UV printing equipment using cylindrical magnets can prevent damage to quality consumable materials (making plates, Squeegees) during printing and improve printing quality by applying technology to prevent product from flipping or standing up when fixing the product by making the magnetic formation of cylindrical magnets form up and down. The development of cylindrical magnets that changed the direction of magnetic force will stabilize the fixing method for metal products made by powder compression, increasing the production capacity for small products. Finally, by studying the power inductor surface UV printing device using cylindrical magnets, it can be differentiated from the spray and deeping methods that were being worked on, production will be greatly improved, and as a result, cost reduction and competitive production will be possible.