• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.05a
• /
• pp.219-223
• /
• 2002

전자부품의 고성능화 고집적화를 위한 표면실장기술의 발전과 환경과 건강에 대한 관심의 증가로 땜납 중의 납의 독성과 그에 따른 납 사용 규제 움직임과 선진국의 법규제에 대응 하여 무연 땜납이 개발되고 있다. 본 연구는 이러한 배경에서 무연 땜납용 볼에 관한 기술정보의 유용성의 제고와 객관적인 비교평가를 위한 표준을 제시하는데 그 목적이 있다. 본 연구에서는 납점용 볼의 표준화 현황을 조사하고, 기업을 대상으로 설문조사를 실시하여 납땜용 볼에 대한 인식과 표준화 현황을 조사하였다. 또, 기존에 납땜용 볼에 관하여 발표되었던 자료들을 조사하여, 유연.무연 납땜용 볼의 품질특성과 그 평가방법을 비교하여 연구하였다. 무연 납땜용 볼은 외관이 거칠고, 융점과 표면장력의 차이로 인하여 젖음성이 떨어지며, 리플로우 조건에 따라 접합부의 높이에 변화가 있으며, 접합강도는 높아지는 특성을 보였으며 접합부의 신뢰성에서도 유연 납땜용 볼과는 많은 차이를 보였다. 이런 무연 땜납의 특성을 감안하여, 몇 가지 품질특성별 평가방법 및 기준을 제시하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.1
• /
• pp.8-18
• /
• 2000

We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.46 no.10
• /
• pp.876-882
• /
• 2018

The purpose of this research is to verify the feasibility of Plastic Ball Grid Array (PBGA), one of the most popular chip packaging types for commercial electronics, under strong random vibration occurred in satellite during launch. Experiment were performed by preparing daisy chained PCB specimen, where large size PBGA were surface mounted, and the PCB was fixed to an aluminum frame which is commonly used to install the electronics parts to satellite. Then the entire sample was fixed to vibration tester. The random vibration power spectrum density employed in the tests were composed of two steps, the acceptance level of 22.7 Grms, and qualification level of 32.1 Grms with given period of time. The test results showed no solder cracks, which provided the strong structural integrity and feasibility evidences of the PBGA packaging to aerospace electronics. Numerical analyses were also performed to calculate the solder stresses and analyze their development mechanism.

• Journal of the Semiconductor & Display Technology
• /
• v.15 no.4
• /
• pp.10-15
• /
• 2016

In this paper, novel ball grid array (BGA) interconnection process using solderable anisotropic conductive adhesives (SACAs) with low-melting-point alloy (LMPA) fillers have been developed to enhance the processability in the conventional capillary underfill technique and to overcome the limitations in the no-flow underfill technique. To confirm the feasibility of the proposed technique, BGA interconnection test was performed using two types of SACA with different LMPA concentration (0 and 4 vol%). After the interconnection process, the interconnection characteristics such as morphology of conduction path and electrical properties of BGA assemblies were inspected and compared. The results indicated that BGA assemblies using SACA without LMPA fillers showed weak conduction path formation such as solder bump loss or short circuit formation because of the expansion of air bubbles within the interconnection area due to the relatively high reflow peak temperature. Meanwhile, assemblies using SACA with 4 vol% LMPAs showed stable metallurgical interconnection formation and electrical resistance due to the favorable selective wetting behavior of molten LMPAs for the solder bump and Cu metallization.

• Journal of the Microelectronics and Packaging Society
• /
• v.27 no.1
• /
• pp.55-65
• /
• 2020

The use of underfill materials in semiconductor packages is not only important for stress relieving of the package, but also for improving the reliability of the package during shock and vibration. However, in recent years, as the size of the package becomes larger and very thin, the use of the underfill shows adverse effects and rather deteriorates the reliability of the package. To resolve these issues, we developed the package using a solid epoxy material to improve the reliability of the package as a substitute for underfill material. The developed solid epoxy was applied to the package of the application processor in smart phone, and the reliability of the package was evaluated using thermal cycling reliability tests and numerical analysis. In order to find the optimal solid epoxy material and process conditions for improving the reliability, the effects of various factors on the reliability, such as the application number of solid epoxy, type of PCB pad, and different solid epoxy materials, were investigated. The reliability test results indicated that the package with solid epoxy exhibited higher reliability than that without solid epoxy. The application of solid epoxy at six locations showed higher reliability than that of solid epoxy at four locations indicating that the solid epoxy plays a role in relieving stress of the package, thereby improving the reliability of the package. For the different types of PCB pad, NSMD (non-solder mask defined) pad showed higher reliability than the SMD (solder mask defined) pad. This is because the application of the NSMD pad is more advantageous in terms of thermomechanical stress reliability because the solderpad bond area is larger. In addition, for the different solid epoxy materials with different thermal expansion coefficients, the reliability was more improved when solid epoxy having lower thermal expansion coefficient was used.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.4
• /
• pp.57-64
• /
• 2012

Ball shear test was performed by test variables such as loading speed and annealing time in order to investigate the effect of surface finishes on the bonding strength of Sn-1.2Ag-0.7Cu-0.4In Pb-free solder. The shear strength increased and the ductility decreased with increasing shear speed. With increasing shear speed, the electroless nickel immersion gold (ENIG) finish showed dominant brittle fracture mode, while organic solderability preservative (OSP) finish showed pad open fracture mode. The shear strength and toughness for both surface finishes decreased with increasing annealing time under the high-speed shear test of 500 mm/s. Typically, the thickness of intermetallic compound increased with increasing annealing time, which means that exposure of brittle fracture became much easier. With increasing annealing time, the both ENIG and OSP finishes exhibited the pad open fracture mode. Overall, ENIG finish showed higher shear strength rather than OSP finish due to its superior barrier stability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.05a
• /
• pp.708-711
• /
• 1999

The Cu/Ni/Au lamellar structure is extensively used as an under bump metallization on silicon file, and on printed circuit board(PCB) pads. Ni is plated Cu by either electroless Ni plating, or electrolytic Ni plating. Unlike the electrolytic Ni plating, the electroless Ni plating does not deposit pure Ni, but a mixture of Ni and phosphorous, because hypophosphite Is used in the chemical reaction for reducing Ni ions. The fracture crack extended at the interface between solder balls of plastic ball grid (PBGA) package and conducting pads of PCB. The fracture is duets to segregation at the interface between Ni$_3$Sn$_4$intermetallic and Ni-P layer. The XPS diffraction results of Cu/Ni/Au results of CU/Ni/AU finishs showed that the Ni was amorphous with supersaturated P. The XPS and EDXA results of the fracture surface indicated that both of the fracture occurred on the transition lesion where Sn, P and Ni concentrations changed.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.36 no.1
• /
• pp.47-54
• /
• 2012

We developed a novel method of fluidic self-assembly to replace the conventional pick-and-place method. This method is cheaper and more effective than the previous method. For this research, we compared mathematical models with experimental results using the parameters of the drag force, the capillary force, and the restoring force for effective chip assembly, and the results for the alignment to the substrate. We obtained a 96.5% attach rate and $5^{\circ}$-misalignment to the substrate in a 500 ${\mu}m$ solder ball.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.10
• /
• pp.687-698
• /
• 2001

This paper presents a three dimensional stacked pad area away (PAA) package configuration as an implementation method of radio frequency (RF) circuits. 224MHz RF circuits of intelligence traffic system(ITS) were constructed with the stacked PAA RF pakage configuration. In the process of manufacturing the stacked PAA RF pakage, RF circuits were partitioned to subareas following their function and operating frequency. Each area of circuits separated to each subunits. The operating characteristics of RF PAA package module and the electrical properties of each subunits were examined. The measurement of electrical parameters for solder balls which were interconnects for stacked PAA RF packages showed that the parasitic capacitance and inductance were 30fF and 120pH, respectively, which might be negligible in PAA RF packaging system. HP 4396B network/spectrum analyzer revealed that the amplification gain of a receiver and transmitter at 224 MHz was 22dB and 27dB, respectively. The gain was 3dB lower than designed values. The difference was probably generated from fabrication process of the circuits by employing commercial standard

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.431-432
• /
• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.