• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 춘계학술대회 논문집
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• pp.843-844
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• 2012

• 반도체디스플레이기술학회지
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• 제23권1호
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• pp.97-103
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• 2024

In this paper, the difference between the S-parameter and the characteristic impedance according to the structural change of the fine pitch coaxial socket was analyzed. A pitch of the probe pin was applied to 0.20mm, and ground pins of different conditions were placed on each of the five signal pins. Insertion loss and reflection loss were analyzed for the coaxial socket of normal structure and the two sockets of the proposed structure. In addition, the difference in characteristic impedance was analyzed using time domain reflectometry. Through the analysis, it was confirmed that the characteristic impedance was improved applying the new structures of the socket at the same pitch

• 한국재료학회지
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• 제18권11호
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• pp.592-596
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• 2008

Spring constants (displacement per unit applied load) of MEMS socket pins of given structures were computed by theoretical analysis and confirmed by the finite element method (FEM). In the theoretical analysis, the displacement of pins was calculated based on the 2-dimensional bending theory of the curved beam. For the 3-dimensional modeling, CATIA was used. After modeling, the raw data were transferred to ANSYS, which was employed in the 3-dimensional analysis for the calculation of the stress and strain and loaddisplacement The theoretical analysis and the FEM results were found to agree, with each showing the spring constants as 63.4 N/m within a reasonable load range. These results show that spring constants can be easily obtained through theoretical calculation without resorting to experiments and FEM analysis for simple and symmetric structures. For the some change of shape and structural stiffness, this theoretical analysis can be applied to MEMS socket pins.

• 한국재료학회지
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• 제18권9호
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• pp.497-502
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• 2008

BGA test sockets failed earlier than the expected life-time due to abnormal signal delay, shown especially at the low temperature ($-50^{\circ}C$). Analysis of failed sockets was conducted by EDX, AES, and XRD. A SnO layer contaminated with C was found to form on the surface of socket pins. The formation of SnO layer was attributed to the repeated Sn transfer from BGA balls to pin surface and instant oxidation of fresh Sn. As a result, contact resistance increased, inducing signal delay. Abnormal signal delay at the low temperature was attributed to the increasing resistivity of Sn oxide with decreasing temperature, as manifested by the resistance measurement of $SnO_2$.

• 한국재료학회지
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• 제22권10호
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• pp.545-551
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• 2012

In semiconductor manufacturing, the circuit integrity of packaged BGA devices is tested by measuring electrical resistance using test sockets. Test sockets have been reported to often fail earlier than the expected life-time due to high contact resistance. This has been attributed to the formation of Sn oxide films on the Au coating layer of the probe pins loaded on the socket. Similar to contact failure, and known as "fretting", this process widely occurs between two conductive surfaces due to the continual rupture and accumulation of oxide films. However, the failure mechanism at the probe pin differs from fretting. In this study, the microstructural processes and formation mechanisms of Sn oxide films developed on the probe pin surface were investigated. Failure analysis was conducted mainly by FIB-FESEM observations, along with EDX, AES, and XRD analyses. Soft and fresh Sn was found to be transferred repeatedly from the solder bump to the Au surface of the probe pins; it was then instantly oxidized to SnO. The $SnO_2$ phase is a more stable natural oxide, but SnO has been proved to grow on Sn thin film at low temperature (< $150^{\circ}C$). Further oxidation to $SnO_2$ is thought to be limited to 30%. The SnO film grew layer by layer up to 571 nm after testing of 50,500 cycles (1 nm/100 cycle). This resulted in the increase of contact resistance and thus of signal delay between the probe pin and the solder bump.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.673-676
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• 2003

In this paper, we designed the embedded system used for wireless LAN communication. Embedded system kernel is made from general linux kernel 2.4.18 by applying the ARM patch (2.4.18-rmk7) and the SA1100 patch(2.4.18-rmk7), then porting board level suitable to target system. The SA-1110 PCMCIA interface provides controls for one PCMCIA card slot with a PSKTSEL pin for support of a second slot. The embedded system requires external logic to complete the PCMCIA socket interface. For dual-voltage support, level shifting buffers are required for all SA-1110 input signals. Hot insertion capability requires that each socket be electrically isolated from each other, and from the remainder of the memory system. embedded system is for socket services approaching PCMCIA socket, detecting number of sockets, sensing insertion and removal, and applying power. It also provides interface with Card services. Embedded system supports Host driver for lucent chips that is installed orinoco driver cross compiled. The meaning can say that is doing wireless LAN communication through wireless LAN in imbedded system.

• 소성∙가공
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• 제15권9호
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• pp.648-653
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• 2006

In this study, the characteristics of Wire Electrical Discharge Machining(WEDM) of the high-hardened mold steel were investigated. WEDM experiments have been carried out based on parameter of wire diameter, pulse on time, pulse off time, feed rate and cycle etc. From the results, the optimized WEDM cycle of RIGOR steel has been revealed as $5{\sim}7$ times. Also, geometrical accuracy of the Core Pin is dependent on WEDM wire radius machining condition and wire chattering.

• 대한전자공학회논문지SD
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• 제47권11호
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• pp.1-5
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• 2010

본 논문에서는 외팔보 배열 구조를 가지는 MEMS 테스트 소켓을 SOI 웨이퍼를 이용하여 개발하였다. 외팔보는 연결부분의 기계적 취약점을 보완하기 위해 모서리가 둥근 형태를 가지고 있다. 측정에 사용 된 BGA IC 패키지는 볼 수 121개, 피치가 $650{\mu}m$, 볼 직경 $300{\mu}m$, 높이 $200{\mu}m$ 을 가지고 있다. 제작된 외팔보는 길이 $350{\mu}m$, 최대 폭 $200{\mu}m$, 최소 폭 $100{\mu}m$, 두께가 $10{\mu}m$인 곡선 형태의 외팔보이다. MEMS 테스트 소켓은 lift-off 기술과 Deep RIE 기술 등의 미세전기기계시스템(MEMS) 기술로 제작되었다. MEMS 테스트 소켓은 간단한 구조와 낮은 제작비, 미세 피치, 높은 핀 수와 빠른 프로토타입을 제작할 수 있다는 장점이 있다. MEMS 테스트의 특성을 평가하기 위해 deflection에 따른 접촉힘과 금속과 팁 사이의 저항과 접촉저항을 측정하였다. 제작된 외팔보는 $90{\mu}m$ deflection에 1.3 gf의 접촉힘을 나타내었다. 신호경로저항은 $17{\Omega}$ 이하였고 접촉저항은 평균 $0.73{\Omega}$ 정도였다. 제작된 테스트 소켓은 향 후 BGA IC 패키지 테스트에 적용 가능 할 것이다.

• 전기학회논문지P
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• 제57권2호
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• pp.181-185
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• 2008

In this paper, we investigates accident actual conditions of electric outlet for low voltage that is used into interior and clear hazardous factor. Electric outlet for general can know that melting of socket-outlet and carbonization of support occur if a contaminant becomes burnout because is flowed in. Existent outlet consists of structure that special quality is good but inflow of a contaminant is easy when is dry. But, waterproof outlet passes silicon layer and have connected structure plug. As developed outlet covers whole surface and back side, interval was shut. Safety pin of developed outlet was established to operate to vertical direction. Therefore, we estimate that contribute on prevention of electrical disaster if use developed outlet to a restaurant, a laundry, a laboratory etc.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.