• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.843-844
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• 2012

• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.97-103
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• 2024

In this paper, the difference between the S-parameter and the characteristic impedance according to the structural change of the fine pitch coaxial socket was analyzed. A pitch of the probe pin was applied to 0.20mm, and ground pins of different conditions were placed on each of the five signal pins. Insertion loss and reflection loss were analyzed for the coaxial socket of normal structure and the two sockets of the proposed structure. In addition, the difference in characteristic impedance was analyzed using time domain reflectometry. Through the analysis, it was confirmed that the characteristic impedance was improved applying the new structures of the socket at the same pitch

• Korean Journal of Materials Research
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• v.18 no.11
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• pp.592-596
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• 2008

Spring constants (displacement per unit applied load) of MEMS socket pins of given structures were computed by theoretical analysis and confirmed by the finite element method (FEM). In the theoretical analysis, the displacement of pins was calculated based on the 2-dimensional bending theory of the curved beam. For the 3-dimensional modeling, CATIA was used. After modeling, the raw data were transferred to ANSYS, which was employed in the 3-dimensional analysis for the calculation of the stress and strain and loaddisplacement The theoretical analysis and the FEM results were found to agree, with each showing the spring constants as 63.4 N/m within a reasonable load range. These results show that spring constants can be easily obtained through theoretical calculation without resorting to experiments and FEM analysis for simple and symmetric structures. For the some change of shape and structural stiffness, this theoretical analysis can be applied to MEMS socket pins.

• Korean Journal of Materials Research
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• v.18 no.9
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• pp.497-502
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• 2008

BGA test sockets failed earlier than the expected life-time due to abnormal signal delay, shown especially at the low temperature ($-50^{\circ}C$). Analysis of failed sockets was conducted by EDX, AES, and XRD. A SnO layer contaminated with C was found to form on the surface of socket pins. The formation of SnO layer was attributed to the repeated Sn transfer from BGA balls to pin surface and instant oxidation of fresh Sn. As a result, contact resistance increased, inducing signal delay. Abnormal signal delay at the low temperature was attributed to the increasing resistivity of Sn oxide with decreasing temperature, as manifested by the resistance measurement of $SnO_2$.

• Korean Journal of Materials Research
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• v.22 no.10
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• pp.545-551
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• 2012

In semiconductor manufacturing, the circuit integrity of packaged BGA devices is tested by measuring electrical resistance using test sockets. Test sockets have been reported to often fail earlier than the expected life-time due to high contact resistance. This has been attributed to the formation of Sn oxide films on the Au coating layer of the probe pins loaded on the socket. Similar to contact failure, and known as "fretting", this process widely occurs between two conductive surfaces due to the continual rupture and accumulation of oxide films. However, the failure mechanism at the probe pin differs from fretting. In this study, the microstructural processes and formation mechanisms of Sn oxide films developed on the probe pin surface were investigated. Failure analysis was conducted mainly by FIB-FESEM observations, along with EDX, AES, and XRD analyses. Soft and fresh Sn was found to be transferred repeatedly from the solder bump to the Au surface of the probe pins; it was then instantly oxidized to SnO. The $SnO_2$ phase is a more stable natural oxide, but SnO has been proved to grow on Sn thin film at low temperature (< $150^{\circ}C$). Further oxidation to $SnO_2$ is thought to be limited to 30%. The SnO film grew layer by layer up to 571 nm after testing of 50,500 cycles (1 nm/100 cycle). This resulted in the increase of contact resistance and thus of signal delay between the probe pin and the solder bump.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.673-676
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• 2003

In this paper, we designed the embedded system used for wireless LAN communication. Embedded system kernel is made from general linux kernel 2.4.18 by applying the ARM patch (2.4.18-rmk7) and the SA1100 patch(2.4.18-rmk7), then porting board level suitable to target system. The SA-1110 PCMCIA interface provides controls for one PCMCIA card slot with a PSKTSEL pin for support of a second slot. The embedded system requires external logic to complete the PCMCIA socket interface. For dual-voltage support, level shifting buffers are required for all SA-1110 input signals. Hot insertion capability requires that each socket be electrically isolated from each other, and from the remainder of the memory system. embedded system is for socket services approaching PCMCIA socket, detecting number of sockets, sensing insertion and removal, and applying power. It also provides interface with Card services. Embedded system supports Host driver for lucent chips that is installed orinoco driver cross compiled. The meaning can say that is doing wireless LAN communication through wireless LAN in imbedded system.

• Transactions of Materials Processing
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• v.15 no.9 s.90
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• pp.648-653
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• 2006

In this study, the characteristics of Wire Electrical Discharge Machining(WEDM) of the high-hardened mold steel were investigated. WEDM experiments have been carried out based on parameter of wire diameter, pulse on time, pulse off time, feed rate and cycle etc. From the results, the optimized WEDM cycle of RIGOR steel has been revealed as $5{\sim}7$ times. Also, geometrical accuracy of the Core Pin is dependent on WEDM wire radius machining condition and wire chattering.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.1-5
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• 2010

We developed a novel micro-electro mechanical systems (MEMS) test socket using silicon on insulator (SOI) substrate with the cantilever array structure. We designed the round shaped cantilevers with the maximum length of $350{\mu}m$, the maximum width of $200{\mu}m$ and the thickness of $10{\mu}m$ for $650{\mu}m$ pitch for 8 mm x 8 mm area and 121 balls square ball grid array (BGA) packages. The MEMS test socket was fabricated by MEMS technology using metal lift off process and deep reactive ion etching (DRIE) silicon etcher and so on. The MEMS test socket has a simple structure, low production cost, fine pitch, high pin count and rapid prototyping. We verified the performances of the MEMS test sockets such as deflection as a function of the applied force, path resistance between the cantilever and the metal pad and the contact resistance. Fabricated cantilever has 1.3 gf (gram force) at $90{\mu}m$ deflection. Total path resistance was less than $17{\Omega}$. The contact resistance was approximately from 0.7 to $0.75{\Omega}$ for all cantilevers. Therefore the test socket is suitable for BGA integrated circuit (IC) packages tests.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.2
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• pp.181-185
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• 2008

In this paper, we investigates accident actual conditions of electric outlet for low voltage that is used into interior and clear hazardous factor. Electric outlet for general can know that melting of socket-outlet and carbonization of support occur if a contaminant becomes burnout because is flowed in. Existent outlet consists of structure that special quality is good but inflow of a contaminant is easy when is dry. But, waterproof outlet passes silicon layer and have connected structure plug. As developed outlet covers whole surface and back side, interval was shut. Safety pin of developed outlet was established to operate to vertical direction. Therefore, we estimate that contribute on prevention of electrical disaster if use developed outlet to a restaurant, a laundry, a laboratory etc.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.