• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.345-355
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• 2014

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

• Advances in aircraft and spacecraft science
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• v.7 no.1
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• pp.79-90
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• 2020

The dynamic coupling between shaker and test-article has been investigated by recent research through the so called Virtual Shaker Testing (VST) approach. Basically a VST model includes the mathematical models of the test-item, of the shaker body, of the seismic mass and the facility vibration control algorithm. The subsequent coupled dynamic simulation even if more complex than the classical hard-mounted sine test-prediction, is a closer representation of the reality and is expected to be more accurate. One of the most remarkable benefits of VST is the accurate quantification of the frequency down-shift (with respect to the hard-mounted value), typically affecting the first lateral resonance of heavy test-items, like medium or large size Spacecraft (S/Cs), once mounted on the shaker. In this work, starting from previous successful VST experiences, the parameters having impact on the frequency shift are identified and discussed one by one. A simplified analytical system is thus defined to propose an efficient and effective way of calculating the lower bound frequency shift through a simple equation. Such equation can be useful to correct the S/C lateral natural frequency measured during the test, in order to remove the contribution attributable to the shaker in use. The so-corrected frequency value becomes relevant when verifying the compliance of the S/C w.r.t. the frequency requirement from the Launcher Authority. Moreover, it allows to perform a consistent post-test correlation of the first lateral natural frequency of S/C FE model.

• The Journal of the Korea Contents Association
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• v.5 no.1
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• pp.229-236
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• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.9-16
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• 2004

For a System-on-a-Chip(SoC) comprised of multiple IP cores, test control techniques have been developed to perform the internal and external test efficiently relying on the various design for testability techniques such as scan and BIST(Built-In Self-Test). However the test area overhead is too expensive to guarantee diverse test link configurations. In this paper, at first we introduce a new flag based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Then a simple test control technique, which can interconnect internal scan chains of different cores, is described with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

• Nuclear Engineering and Technology
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• v.50 no.8
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• pp.1298-1305
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• 2018

The use of System-on-Chip (SoC) solutions in the design of on-board data handling systems is an important step towards further miniaturization in space. However, the Total Ionizing Dose (TID) and Single Event Effects (SEE) characterization of these complex devices present new challenges that are either not fully addressed by current testing guidelines or may result in expensive, cumbersome test configurations. In this paper we report the test setups, procedures and results for TID testing of a SoC microcontroller both using standard $^{60}Co$ and low-energy protons beams. This paper specifically points out the differences in the test methodology and in the challenges between TID testing with proton beam and with the conventional gamma ray irradiation. New test setup and procedures are proposed which are capable of emulating typical mission conditions (clock, bias, software, reprogramming, etc.) while keeping the test setup as simple as possible at the same time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.105-116
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• 2008

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, we propose an efficient test access mechanism that exploits an on/off-chip bus bridge for the Advanced High-performance Bus (AHB) and Peripheral Component Interconnect (PCI) bus. The test application time is considerably reduced by providing dedicated test stimuli input paths and response output paths, and by excluding the bus direction tumaround delays. Experimental results show that area overhead and testing times are considerably reduced in both functional and structural test modes. The proposed technique can be a lied to the other types of on/off-chip bus bridges.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.75-78
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• 2001

Recently, the HFPD measurement testing is widely used in partial discharge measurement of HV machines because HFPD measurement testing receives less influence of external noise and has a merit of good sensitivity. Also HFPD testing is able to offer the judgement standard of degradation level of HV machine and can detect discharge signals in live-line. Therefore it is very useful method compare to previous conventional PD testing method and effective diagnosis method in power transformer that requires live-line diagnosis. But partial discharges have very complex characteristics of discharge pattern so it is required continuous research to development of precise analysis method. In recent, the study of partial discharge is carrying out discover of initial defect of power equipment through condition diagnosis and system development of degradation diagnosis using HFPD(High Frequency Partial Discharge) detection. In this study, simulated transformer is manufactured and HFPD occurred from transformer is measured with broad band antenna in real time, the degradation grade of transformer is analyzed through produced patterns in simulated transformer according to applied voltages.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.93-100
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• 2004

Test scheduling of SoC (System-on-a-chip) is very important because it is one of the prime methods to minimize the testing time under limited power consumption of SoC. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoC is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position in test space to minimize the idling test time of test resources. The efficiency of proposed algorithm is confirmed by experiment using ITC02 benchmarks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.44-54
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• 2011

The goal of this paper is reducing the test time for AMBA-based SoC. To achieve this goal, the design technique that can test several cores concurrently by reusing AMBA as TAM is proposed. The additional control logic for structural parallel core test is minimized by reusing TIC which is originally used for functional test of AMBA. SoC reliability and test time reduction can be significantly achieved with the concurrent core test technique as well as functional test.

• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.