• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.52 no.3
• /
• pp.137-143
• /
• 2003

The degree of contamination on outdoor insulator is ons of the most importance factor to determine the pollution level of outdoor insulation, and the sea salt is known as the most dangerous pollutant. As shown through the preceding study, the generation of salt pollutant and the pollution degree of outdoor insulator have a close relation with meteorological conditions, such as wind velocity, wind direction, precipitation and so fourth. So, in this paper, we made an investigation on the prediction method, a statistical estimation technique for equivalent salt deposit density of outdoor insulator with multiple linear regression analysis. From the results of the analysis, we proved the superiority of the prediction method in which the variables had a very close(about 0.9) correlation coefficient. And the results could be applied to establish the Pollution Prediction System for power utilities, and the system could provide an invaluable information for the design and maintenance of outdoor insulation system.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.14 no.2
• /
• pp.201-206
• /
• 2004

This study attempted to develop a speech recognition module applied to a wheelchair for the physically handicapped. In the proposed speech recognition module, TMS320C32 was used as a main processor and Mel-Cepstrum 12 Order was applied to the pro-processor step to increase the recognition rate in a noisy environment. DTW (Dynamic Time Warping) was used and proven to be excellent output for the speaker-dependent recognition part. In order to utilize this algorithm more effectively, the reference data was compressed to 1/12 using vector quantization so as to decrease memory. In this paper, the necessary diverse technology (End-point detection, DMA processing, etc.) was managed so as to utilize the speech recognition system in real time

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.569-570
• /
• 2008

This paper proposed a new arbitration method in arbiter which is one of bus system components for the design of SoC. Considering compatibility between IP and bus system, the performance of bus system can change the performance of SoC chip. The proposed arbitration method achieved the performance improvement with high efficiency depending on the environment in use.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.8 no.1
• /
• pp.117-123
• /
• 2012

This paper implements mobile Worldwide Interoperability for Microwave Access (WiMAX) receiver using Software Defined Radio (SDR) technology. SDR system is difficult to implement on the mobile handset because of restrictions that are computing power and under space constraints. The implemented receiver processes mobile WiMAX software modem on Open Multimedia Application Platform (OMAP) System on Chip (SoC) and Field Programmable Gate Array (FPGA). OMAP SoC is composed of ARM processor and Digital Signal Processor (DSP). ARM processor supports Single Instruction Multiple Data (SIMD) instruction which could operate on a vector of data with a single instruction and DSP is powerful image and video accelerators. For this reason, we suggest the possibility of SDR technology in the mobile handset. In order to verify the performance of the mobile WiMAX receiver, we measure the software modem runtime respectively. The experimental results show that the proposed receiver is able to do real-time signal processing.

• Proceedings of the KSR Conference
• /
• 2008.06a
• /
• pp.572-578
• /
• 2008

As the railway transportation is getting faster and its operation speed has increased rapidly, its signal control has been complicated. For real time signal processing it is very important to prohibit any critical error from causing the system to malfunction. Therefore, handling complicated signals effectively while maintaining fault-tolerance capability is highly expected in modern railway transportation industry. In this paper, we suggest an SoC (Sytem-on-Chip) design method to integrate these complicated signal controlling mechanism with fault tolerant capability in a single chip. We propose an SoC solution which contains a high performance 32-bit embedded processor, digital filters and a PWM unit inside a single chip to implement ATO's, ATC's, ATP's and ATS's digital signal-processing units. We achieve an enhanced reliability against the calculation error by adding fault tolerance features to ensure the stability of each module.

• The Journal of the Korea Contents Association
• /
• v.9 no.2
• /
• pp.27-35
• /
• 2009

In this paper, we present result of embedded system based H.264/SVC decoder circuit design and system implementation. To deal with the standardized H.264/SVC functionalities, the presented SVC decoder system is consist of hardware engine design and software with ARM core processor. In order to improve the feasibility and applicability, and reduce the decoder complexity, the implemented system is constructed with only the consideration of IPPP structure scalability without using the full B-picture architecture. Finally, we will show the decoding image result using the designed H.264/SVC decoder system.

• ETRI Journal
• /
• v.36 no.2
• /
• pp.293-300
• /
• 2014

As the system-on-chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.1
• /
• pp.683-690
• /
• 2015

Two basic FFT(Fast Fourier Transform) algorithms are the DIT(Decimation-In-Time) and the DIF (Decimation-In-Frequency). In spite of the advantage of the DIT algorithm is to generate a sequential output, various structures have not been made. In this paper, a new DIT Radix-4 FFT butterfly structure are proposed and implemented using Verilog coding. Through synthesis, it is shown that the 64-point FFT is implemented by 6.78 million gates. Since the proposed FFT structure has the advantage of a sequential output, it can be used in OFDM communication SoC(System on a Chip) which need a high speed FFT output.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.9
• /
• pp.26-32
• /
• 2008

The conventional shared bus architecture is capable of processing only one data transaction in same time. In this paper, we propose the NAWM (No Arbitration Wild Master) bus architecture that is capable of processing several data transactions in same time. After designing the master and the slave wrappers of NAWM bus architecture about AMBA system, we confirm that most of IPs of AMBA system can be a lied without modification and the added timing delay can be neglected. from simulation we deduce that more than 50% parallel processing is possible when several masters initiate slaves in NAWM bus architecture.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.14 no.5
• /
• pp.991-1000
• /
• 2019

The flying-disc game has started since 1940. It has been spreading rapidly in Korea since 2007, mainly in elementary schools. Additionally, as sports science has been developed, research on flying discs has been continued to build a monitoring system for technological improvement and efficiency. In this paper, we acquire information on the user's flying-disc using 9-axis motion sensor and GPS. Then we propose a method for wireless transmission using Bluetooth 5.0. Specifically, the HW platform was designed and implemented not only to monitor a real-time data but also to compare and analyze rotational speed, flight trajectory, and a count of disc rotation through post-processing.