• Title/Summary/Keyword: SoC System

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A Platform-Based SoC Design for Real-Time Stereo Vision

  • Yi, Jong-Su;Park, Jae-Hwa;Kim, Jun-Seong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.2
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    • pp.212-218
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    • 2012
  • A stereo vision is able to build three-dimensional maps of its environment. It can provide much more complete information than a 2D image based vision but has to process, at least, that much more data. In the past decade, real-time stereo has become a reality. Some solutions are based on reconfigurable hardware and others rely on specialized hardware. However, they are designed for their own specific applications and are difficult to extend their functionalities. This paper describes a vision system based on a System on a Chip (SoC) platform. A real-time stereo image correlator is implemented using Sum of Absolute Difference (SAD) algorithm and is integrated into the vision system using AMBA bus protocol. Since the system is designed on a pre-verified platform it can be easily extended in its functionality increasing design productivity. Simulation results show that the vision system is suitable for various real-time applications.

A System-on-a-Chip Design for Digital TV

  • Rhee, Seung-Hyeon;Lee, Hun-Cheol;Kim, Sang-Hoon;Choi, Byung-Tae;Lee, Seok-Soo;Choi, Seung-Jong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.4
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    • pp.249-254
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    • 2005
  • This paper presents a system-on-a-chip (SOC) design for digital TV. The single LSI incorporates almost all essential parts such as CPU, ISO/IEC 11172/13818 system/audio/video decoders, a video post-processor, a graphics/OSD processor and a display processor. It has analog IP's inside such as video DACs, an audio PLL, and a system PLL to reduce the system-level implementation cost. Descramblers and Smart Card interface are included to support widely used conditional access systems. The video decoder can decode two video streams simultaneously. The DSP-based audio decoder can process various audio coding specifications. The functional blocks for video quality enhancement also form outstanding features of this SoC. The SoC supports world-wide major DTV services including ATSC, ARIB, DVB, and DIRECTV.

Implementation to human-computer interface system with motion tracking using OpenCV and FPGA (FPGA와 OpenCV를 이용한 눈동자 모션인식을 통한 의사소통 시스템)

  • Lee, Hee Bin;Heo, Seung Won;Lee, Seung Jun;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2018.05a
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    • pp.696-699
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    • 2018
  • This paper introduces a system that enables pupillary tracing and communication with patients with amyotrophic lateral sclerosis (ALS) who can not move free. Face and pupil are tracked using OpenCV, and eye movements are detected using DE1-SoC board. We use the webcam, track the pupil, identify the pupil's movement according to the pupil coordinate value, and select the character according to the user's intention. We propose a system that can use relatively low development cost and FPGA can be reusable, and can select a text easily to mobile phone by using Bluetooth.

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The VoIP System on Chip Design and the Test Board Development for the Function Verification (VoIP 시스템 칩 설계 및 기능 검증용 보드 개발)

  • 소운섭;황대환;김대영
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2003.10a
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    • pp.990-994
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    • 2003
  • This paper describes the VoIP(Voice over Internet Protocol) SoC(System on Chip) Design and the test board development for the function verification to support voice communication services using Internet. To implement the simple system of configuration, we designed the VoIP SoC which have ARM922T of 32bit microprocessor, IP network interface, voice signal interface, various user interface function. Also we developed test program and communication protocol to verify the function of this chip. We used several tools of design and simulation, developed and tested a test board with Excalibur which includes ARM922T microprocessor and FPGA.

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Test Scheduling Algorithm of System-on-a-Chip Using Extended Tree Growing Graph (확장 나무성장 그래프를 이용한 시스템 온 칩의 테스트 스케줄링 알고리듬)

  • 박진성;이재민
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.3
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    • pp.93-100
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    • 2004
  • Test scheduling of SoC (System-on-a-chip) is very important because it is one of the prime methods to minimize the testing time under limited power consumption of SoC. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoC is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position in test space to minimize the idling test time of test resources. The efficiency of proposed algorithm is confirmed by experiment using ITC02 benchmarks.

Design and Verification of IEEE 802.11a Baseband Processor (IEEE 802.11a 기저대역 프로세서의 설계 및 검증)

  • Kim, Sang-In;Kim, Su-Young;Seo, Jung-Hyun;Yun, Tae-Il;Lee, Je-Hoon;Cho, Kyoung-Rok
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.6 s.360
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    • pp.9-17
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    • 2007
  • This paper shows an implementation of the baseband processor compliant with the IEEE 802.11a standard. Some innovative techniques are proposed to fulfill the mandatory requirements of the standard. For verification and analysis of this design, we use a Platform-based SoC (system on chip) environment. The entire system consists of test-board for the baseband processor chip and the SoC platform for implementing MAC (medium access control).

Wireless Communication System for T/C based on DSRC (DSRC 기반의 T/C 무선통신 시스템 개발)

  • 성창우;강대성
    • Journal of Korean Port Research
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    • v.14 no.3
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    • pp.313-319
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    • 2000
  • In this paper, we proposed the model of wireless communication for ACTS using DSRC and the DSRC system for T/C. The proposed wireless communication model is how to join with DSRC and other wireless communication in port. The DSRC system for T/C is the first application to the unit of port Facilities Automation on stacking area. The DSRC system is communicated between OBE and RSE using 5.8Hz ISM band frequency. The previous works of DSRC applications are gate automation. In these cases, the road trackers are difficult to obtain information of the port in the stacking area. So we used the DSRC for the wireless communication for the port Facilities Automation. Using DSRC, the load trackers obtain more information in the port and contacts to ITS on back-roads of port. The proposed communication system is serviced to reelection of port statistics.

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Synchronousness of Multi-Object Intelligent C System Using Fuzzy Controller (퍼지 제어기를 이용한 다 개체 지능 제어 시스템의 동기화 제어)

  • 문희근;김영탁;공석민;김관형;이상배
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2001.12a
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    • pp.177-180
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    • 2001
  • The subject of this paper is to efficient Pm duty contort for two DC motor synchronousness in the system. Fuzzy controller have been successfully applied to many uncertain and complex industrial plant. So, It adapted fuzzy controller using compositional fuzzy rule so that change PH duty for speed control if the length of destination is different, And for unknow plant, it is the study to make the unknow transfer function system with fuzzy control method. This controller has been successfully applied to Pm duty control for the system synchronousness.

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Development and Verification of SoC Platform based on OpenRISC Processor and WISHBONE Bus (OpenRISC 프로세서와 WISHBONE 버스 기반 SoC 플랫폼 개발 및 검증)

  • Bin, Young-Hoon;Ryoo, Kwang-Ki
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.1
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    • pp.76-84
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    • 2009
  • This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

A Study of Building a Model for Tactical C4I System (전술 C4I체계 모델 구축에 관한 연구)

  • Kim, Ho-Jin;Lee, Sang-Kook;Kwon, Young-Sik
    • IE interfaces
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    • v.12 no.2
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    • pp.193-204
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    • 1999
  • Development of high technology especially in telecommunication and precise weapon systems will impact the future battle field environment. So it is not difficult to anticipate the environment of military command and control system will be changed rapidly. Considering these future battle field environment, military needs automated C4I (Command, Control, Communication, Computer and Intelligence) system, namely real time decision support system which is combined high technologies. Most of advanced countries have been studied and developed these kinds of systems and already applied these systems in real military operations. In order to take a military initiative in Korea peninsula it is essential to catch up with this trend and procure C4I system. The purpose of this research is to present the method and the direction of optimal C4I system development model. First we survey the related theory about C4I systems. Second we present the conceptual framework for C4I system concept development. Third we model the system using Timed Petri-Net and perform simulation. Finally we analyze the through-put time and suggest alternatives. If we model using the real organization structure, operational tasks and various situations then optimal C4I system would be developed.

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