• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.85-95
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• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.1
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• pp.33-39
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• 2009

This paper presents a new secure scan design technique to protect secret key from scan-based side channel attack for an Advanced Encryption Standard(AES) core embedded on an System-on-a-Chip(SoC). Our proposed secure scan design technique can be applied to crypto IF core which is optimized for applications without the IP core modification. The IEEE1149.1 standard is kept, and low area and power consumption overheads and high fault coverage can be achieved compared to the existing methods.

• ETRI Journal
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• v.31 no.6
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• pp.795-802
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• 2009

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT-DMB) baseband receiver SoC. The AT-DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T-DMB system; therefore, a conventional T-DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT-DMB baseband receiver SoC is fabricated using 0.13 ${\mu}m$ technology and shows successful operation with a 50 mW power dissipation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.9-16
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• 2004

For a System-on-a-Chip(SoC) comprised of multiple IP cores, test control techniques have been developed to perform the internal and external test efficiently relying on the various design for testability techniques such as scan and BIST(Built-In Self-Test). However the test area overhead is too expensive to guarantee diverse test link configurations. In this paper, at first we introduce a new flag based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Then a simple test control technique, which can interconnect internal scan chains of different cores, is described with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.995-998
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• 2005

This paper proposes a new SoC (System-on-Chip)-based automatic compensation circuit (ACC) for 5GHz low noise amplifier (LNA). This circuit is extremely useful for today's RF IC (Radio Frequency Integrated Circuit) devices in a complete RF transceiver environment. The circuit contains RF BIST (Built-ln Self-Test) circuit, Capacitor Mirror Banks (CMB) and digital processing unit (DPU). The ACC automatically adjusts performance of 5GHz LNA by the processor in the SoC transceiver when the LNA goes out of the normal range of operation.

• 전자공학회논문지 IE
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• v.46 no.2
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• pp.46-52
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• 2009

The manufacturing system was used to communicate between controller and GUI system by RS232C. The controller is deal with processing the equipments such as cylinders, motors, sensors, and so on. The Gill system received the signal from actuator controller by direct communication ways, RS232C, and presented the data to user to analyze the all of status for manufacturing system. In this point, it is important that communication use the RS232C. The way is helpful to be able to reduce cost, have simple structure, and easily maintain the stable communication status. Otherwise, the way has some problem to loss signal or data under the high speed communication. So it needs to complement the communication process to without loss data. In this research, we made the communication algorithm and implement the process to reduce losing data when it send or receive the signal using RS232C between controller and manufacturing system.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1998.10a
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• pp.166-170
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• 1998

Classification and Coding(C&C) systems as a core of design information management have been accomplished by many studies in terms of design and manufacturing attribute based on Group Technology. Those are very difficult to apply in make-to-order(MTO) manufacturing because the environment of MTO has various characteristics of product, many licensors, engineering change, insufficiency of integrated management system for codes and so on. This paper presents a suitable C&C system to MTO manufacturing which consider management level and drawing.

• Journal of the Korean Chemical Society
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• v.35 no.4
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• pp.324-328
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• 1991

The Li$_2SO_4$ system containing various mol${\%}$ of CaSO$_4$ were synthesized. The structure and the electrical conduction of these system were studied at the temperature from 20 to 700$^{\circ}C$. In the region of CaSO$_4$ mol ratio higher than 0.05, it could be confirmed that Li$_2SO_4-CaSO_4$ system does not form solid solution. Due to the substituted Ca$^{2+}$, the transition temperature (monoclinic to cubic) is shifted to the low temperature. The ionic conduction of monoclinic Li$_2SO_4-CaSO_4$ increased with increasing lithium vacancy which was produced by substituted Ca$^{2+}$, but that fcc Li$_2SO_4-CaSO_4$ was not influenced by the substituted Ca$^{2+}$ ion.

• Journal of the Korean Society for Precision Engineering
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• v.25 no.8
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• pp.37-44
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• 2008

Nowadays, the increasing global competition forces manufacturer to reduce the cost and time for implementation of manufacturing system. The AR(augmented reality) technology as a new human-machine interface introduces a noteworthy perspective for a new manufacturing system design. Using AR technology, a physically existing production environment can be superimposed with virtual planning objects. Therefore, the planning tasks can be validated without modeling the surrounding environment of the production domain during short process planning time. In this paper, we introduce the construction of AR browser and determine the optimal environment parameters for field application of AR system through lots of tests. And, many methods such as multi-marker coordinate system, division of virtual objects and so on, are proposed in order to solve the problems suggested from initial field test. Based on these tests and results, the test-bed of C/Pad assembly system is configured and robot program for C/Pad assembly is generated based on AR system.

• ETRI Journal
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• v.38 no.3
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• pp.479-486
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• 2016

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.