• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.1
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• pp.156-160
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• 2011

This paper describes the design and implementation of a System-on-a-Chip (SoC) for pattern recognition to use in embedded applications. The target Soc consists of LEON2 core, AMBA/APB bus-systems and custom-designed accelerators for Gaussian Pyramid construction, lighting compensation and histogram equalization. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, a pattern recognition application is performed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.198-206
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• 2011

This paper presents a new programmable compensation circuit (PCC) for a System-on-Chip (SoC). The PCC is integrated with $0.18-{\mu}m$ BiCMOS SiGe technology. It consists of RF Design-for-Testability (DFT) circuit, Resistor Array Bank (RAB) and digital signal processor (DSP). To verify performance of the PCC we built a 5-GHz low noise amplifier (LNA) with an on-chip RAB using the same technology. Proposed circuit helps it to provide DC output voltages, hence, making the RF system chain automatic. It automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation. The PCC also compensates abnormal operation due to the unusual PVT (Process, Voltage and Thermal) variations in RF circuits.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.417-419
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• 2004

Because of the demands for high performance and high integrated system, the needs for optimal platform becomes more importance. Optimal platform can handle more data effectively with same resources. AMBA(Advanced Microprocessor Bus Architecture)$^{TM}$ defines on-chip communication standard for designing high performance embedded micro-controllers. It is consisted of AHB, ASB and APB. It can support fast implementation and reliability in system that is composed with reusable IPs. DMAC is one of master in system and generate master signals of AHB to communicate data from one slave(peripheral or memory) to another slave. It can reduce burden of CPU and increase system performance. We designed DMAC based on AMBA and it supports 13 Channels. Each channel can be controlled by software program. It decides channel's priority using round-robin method. It can support P2P, P2M, M2P and P2P communication.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1470-1476
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• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.

• Journal of Power System Engineering
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• v.20 no.3
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• pp.17-21
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• 2016

The corrosion behavior of aluminum alloys in the $H_2SO_4$ solution was investigated based on potentiodynamic techniques. Electrochemical properties, such as corrosion potential($E_c$), passive potential($E_p$), corrosion current density($I_c$), corrosion rate(mpy), of Al-Mg-Si, Al-Cu-Si and Al-Si alloys were characterized at room temperature. Passive aluminum oxide film, which including $Al_2(SO_4)_3$ and $3Al_2O_34SO_38H_2O$, were uniformly formed on the surface via the reaction of Al with $SO{_3}^{2-}$ or $SO{_4}^{2-}$ ions in the $H_2SO_4$ solution and the dependence of the corrosion behavior on the alloying element was discussed. The selective leaching of alloy element increased with increasing Cu content in the aluminum alloys.

• Journal of Korea Multimedia Society
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• v.12 no.5
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• pp.617-632
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• 2009

In this paper we propose a technique of implementing the reconfigurable network protocol stack that allows for partitioning network protocol functions into software and hardware tasks on a SoC (System on Chip) platform. Additionally, we present a method that guarantees the deadline of both an individual task and messages exchanging among tasks in order to meet the deadline of real-time multimedia and networking services. The proposed real-time message exchange method guarantees the deadline of messages generated by multimedia services that are required to meet the real-time properties of multimedia applications. After implementing the networking functions of TCP/IP protocol suite into hardware and software tasks, we verify and validate their performance on the SoC platform. Experimental results indicate that the proposed technique improves the performance of TCP/IP protocol suit as well as application service satisfaction in application-specific real-time.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• Journal of Periodontal and Implant Science
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• v.38 no.sup2
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• pp.335-342
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• 2008

Purpose: Cytolethal distending toxin (CDT) considered as a key factor of localized aggressive periodontitis, endocarditis, meningitis, and osteomyelitis is composed of five open reading frames (ORFs). Among of them, the individual role of CdtA and CdtC is not clear; several reports presents that CDT is an AB2 toxin and they enters the host cell via clathrin-coated pits or through the interaction with GM3 ganglioside. So, CdtA, CdtC, or both seem to be required for the delivery of the CdtB protein into the host cell. Moreover, recombinant CDT was suggested as good vaccine material and antibody against CDT can be used for neutralization or for a detection kit. Materials and Methods: We constructed the pET28a-cdtC plasmid from Aggregatibacter actinomycetemcomitans Y4 by genomic DNA PCR and expressed in BL21 (DE3) Escherichia coli system. We obtained the antibody against the recombinant CdtC in mice system. Using the anti-CdtC antibody, we test the native CdtC detection by ELISA and Western Blotting and confirm the expression time of native CdtC protein during the growth phase of A. actinomycetemcomitans. Results: In this study we reconstructed CdtC subunit of A. actinomycetemcomitans Y4 and generated the anti CdtC antibody against recombinant CdtC subunit expressed in E. coli system. Our anti CdtC antibody can be interacting with recombinant CdtC and native CDT in ELISA and Western system. Also, CDT holotoxin existed at 24h but not at 48h meaning that CDT holotoxin was assembled at specific time during the bacterial growth. Conclusion: In conclusion, we thought that our anti CdtC antibody could be used mucosal adjuvant or detection kit development, because it could interact with native CDT holotoxin.

• Journal of IKEEE
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• v.13 no.2
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• pp.101-107
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• 2009

Growth in the VLSI process and design technology is resulting into a continuous increase in the number of IPs on a chip to form a system. Because of many IPs on a single chip, efficient communication between IPs is essential. We propose a dynamically reconfigurable 3-layer bus structure which can adapt to the pattern of data transmission to achieve an efficient data communication between various IPs. The proposed 3-layer bus can be reconfigured to multi-single bus mode, and single-multi bus mode, thus providing the benefits of both single-bus and multi-bus modes. Experimental results show that the flexibility of the proposed bus structure can reduce data transmission time compared to the conventional fixed bus structure. We incorporated the proposed bus structure in a JPEG system and verified that the proposed structure achieved an average of 22% improvement in time over the conventional fixed bus structure.