• IEIE Transactions on Smart Processing and Computing
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• 제5권1호
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• pp.55-62
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• 2016

In this paper, we propose a hybrid multi.system-on-chip (H-MSoC) architecture that provides a high-flexibility system in a rapid development time. The H-MSoC approach provides a flexible system-on-chip (SoC) architecture that is easy to configure for physical- and application-layer development. The physical- and application-layer aspects are dynamically designed and modified; hence, it is important to consider a design methodology that supports rapid SoC development. Physical layer development refers to intellectual property cores or other modular hardware (HW) development, while application layer development refers to user interface or application software (SW) development. H-MSoC is built from multi-SoC architectures in which each SoC is localized and specified based on its development focus, either physical or application (hybrid). Physical HW development SoC is referred to as physical-SoC (Phy-SoC) and application SW development SoC is referred to as application-SoC (App-SoC). Phy-SoC and App-SoC are connected to each other via Ethernet. Ethernet was chosen because of its flexibility, high speed, and easy configuration. For prototyping, we used a LEON3 SoC as the Phy-SoC and a ZYNQ-7000 SoC as the App-SoC. The proposed design was proven in real-time tests and achieved good performance.

• 한국멀티미디어학회논문지
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• 제19권2호
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• pp.122-127
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• 2016

This paper propose implementation method of SoC system for efficient depth image segmentation. SoC systems are combined platform in the form of the Software and Hardware IP. In order to perform effectively, the user to determine the operation of the configuration of each part. In this paper, we implemented a segmentation of depth images taken by the infrared sensor at APU of SoC system. The proposed method efficiently implements high performance and low power in SoC system. Proposed method that using software parts of SoC system is capable to use at several depth image processing systems.

• 전기학회논문지
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• 제58권10호
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• 대한임베디드공학회논문지
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• 제2권1호
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• pp.24-30
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• 2007

According to development of wireless communication technologies, we need not only high data rate but low data rate system of low power consumption. This low data rate system is utilized in the field of home automation, health care, sensoring and monitoring, etc. IEEE 802.15.4 LR-WPAN system is the best choice for realizing ubiquitous networking system. In this paper SoC Architecture for IEEE 802.15.4 Low Rate WPAN is designed. IEEE 802.15.4 Low Rate WPAN system serves the functions and realization of home area network. We propose the SoC architecture for 868/915MHz frequency band of IEEE 802.15.4 Low Rate WPAN system. The key issue is to design SoC architecture which provides the function of Low Rate WPAN system to meet the requirement of IEEE 802.15.4 standards.

• 기술혁신학회지
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• 제11권4호
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• pp.565-591
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• 2008

산업혁신체제론과 공급체인분석을 분석방법론으로 하는 본 연구는 대만과의 비교 관점에서 국내 IT SoC산업의 혁신체제 발전방안을 분석했다. 대만 IT SoC산업은 정부의 국내기업 육성정책하에서 신죽과학산업단지의 조성 이후 급속한 성장을 했다. 대만 IT SoC산업의 공급체인 내에서 파운드리업체와 팹리스업체 간 장기적인 협력네트워트는 양자의 동반 성장을 이끌고 있다. 이를 토대로 해서 대만 IT SoC산업은 다양성 창조와 선택의 과정을 거쳐, 공진화의 가능성을 열어놓고 있다. 반면 국내 IT SoC산업은 공급체인 내에서 팹리스업체와 파운드리업체 간 협력네트워크가 구축되지 않은 가운데, 최근 팹리스업체와 시스템업체 간 협력네트워크도 붕괴되고 있기 때문에 공진화의 가능성은 제약되어 있다. 이를 시스템 실패의 관점에서 보면, 국내 IT SoC산업은 행위자들의 협력 부족으로 보완적 자산이 활용되지 않고 상호보완적 학습이 저지되는 상호작용 실패가 나타나고 있음을 의미한다. IT SoC산업에서는 공급체인의 효율화가 경쟁력의 핵심이기 때문에 상호작용 실패를 보정하는 것이 국내 IT SoC산업의 핵심과제로 제기되고 있다. 국내 현실을 고려해 볼 때, 파운드리업체들의 경쟁력이 워낙 취약하기 때문에 팹리스업체와 파운드리업체 간 협력 네트워크 구축은 상당기간 불가능할 것이다. 그러므로 상호작용 실패의 보정은 팹리스업체와 시스템업체 간 협력네트워크의 강화에 초점을 맞추어야 한다. 이를 위한 구체적인 방안으로서 공동개발의 확대, 가교 조직의 활성화, 지분참여의 세 가지가 제시될 수 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 D
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• pp.2313-2315
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• 2003

This paper presents the development methods which Samsung GPS baseband chip is called S3E4510X. Specification of S3E4510X and design methodology of baseband architecture is presented with a study of their effects. Also GPS core block and software are described in detail. We designed and implemented the test board with RF module for evaluating performance via static test dynamic test and each performance factors using live signal and CPS simulator. Test results show that our development GPS baseband chip have effectively performance for mobile handset Location Based Service (LBS) and its practical use for navigation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.229-236
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• 2005

This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.

• 한국지능시스템학회논문지
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• 제14권4호
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• pp.512-516
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• 2004

상황인식(context-aware)은 인간-컴퓨터 상호작용의 단점을 극복하기 위한 방범으로써 많은 주목을 받고 있다. 이 논문에서는 SoC(System-on-a-Chip)로 구현될 수 있는 상황인식 시스템 구조를 제안한다. 제안한 구조는 센서 추상화, 컨텍스트 변경에 대한 통지 메커니즘, 모듈식 개발, if-then 규칙을 이용한 쉬운 서비스 구성과 유연한 상황인식 서비스 구현을 지원한다. 이 구조는 통신 모듈, 처리 모듈, 블랙보드를 포함하는 SoC 마이크로프로세서 부분과 규칙 기반 시스템 모듈을 구현한 하드웨어로 구성된다. 규칙 기반 시스템 하드웨어는 모든 규칙의 조건부에 대해 매칭 연산을 병렬로 수행하고, 규칙의 결론부는 마이크로프로세서에 내장된 행위 모듈을 호출함으로써 작업을 수행한다. 제안한 구조의 SoC 시스템의 규칙의 매칭부분은 SystemC SoC 개발 환경에서 설계하여 구조의 타당성을 확인하였고, 마이크로프로세서에 내장될 행위모듈에 대해서는 소프트웨어적으로 타당성을 확인하였다. 제안한 SoC 기반의 상황인식 시스템 구조는 주거 환경에서 컨텍스트를 인식하여 노인을 보조하는 지능형 이동 로봇 등에 적용될 수 있을 것으로 기대된다.

• 한국ITS학회:학술대회논문집
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• 한국ITS학회 2003년도 제2회 정기총회 및 추계학술대회
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• pp.48-51
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• 2003

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.89-101
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• 2005

Research on highly abstracted system modeling and simulation has received a great deal of attention as of the concept of platform based design is becoming ubiquitous. From a practical design point of view, such modeling and simulation must consider the following: (i) fast simulation speed and cycle accuracy, (ii) early availability for early stage software development, (iii) inter-operability with external tools for software development, and (iv) reusability of the models. Unfortunately, however, all of the previous works only partially addresses the requirements, due to the inherent conflicts among the requirements. The objective of this study is to develop a new system design methodology to effectively address the requirements mentioned above. We propose a new transaction-level system modeling methodology, called ViP (Virtual Platform). We propose a two-step approach in the ViP method. In phase 1, we create a ViP for early stage software development (before RTL freeze). The ViP created in this step provides high speed simulation, lower cycle accuracy with only minor modeling effort.(satisfying (ii)). In phase 2, we refine the ViP to increase the cycle accuracy for system performance analysis and software optimization (satisfying (i)). We also propose a systematic ViP modeling flow and unified interface scheme based on utilities developed for maximizing reusability and productivity (satisfying (ii) and (iv)) and finally, we demonstrate VChannel, a generic scheme to provide a connection between the ViP and the host-resident application software (satisfying (iii)). ViP had been applied to several System-on-a-chip (SoC) designs including mobile applications, enabling engineers to improve performance while reducing the software development time by 30% compared to traditional methods.