• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.71-76
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• 2007

The effect of crosstalk errors is most significant in high-performance circuits. This paper presents effective test patterns for SoC and Board level interconnects considering actual effective aggressors. Initially '6n' algorithm, where 'n' is the total number of interconnect nets, is analyzed to detect and diagnose 100% crosstalk faults. Then, more efficient algorithm is proposed reducing the number of test patterns significantly while maintaining complete crosstalk fault coverage.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.39-49
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• 2006

This paper proposes an efficient verification environment of PCI Express controller that is the future I/O interface. This verification environment consists of a test vector generator, a test bench, and two abstract memories. We also define the assembler set to generate the verification scenarios. In this paper, we propose the random test environment which consists of a random vector generator, a .simulator part, and a compare engine. This verification methodology is useful to find the special errors which are not detected by the basic-behavioral test and hardware-design test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.73-82
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• 2005

Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Therefore, this paper proposes a new test data compression/decompression method for low power testing. The method is based on analyzing the factors that influence test parameters: compression ratio, power reduction and hardware overhead. To improve the compression ratio and the power reduction ratio, the proposed method is based on Modified Statistical Coding (MSC), Input Reduction (IR) scheme and the algorithms of reordering scan flip-flops and reordering test pattern sequence in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data, not $T_{diff}$, and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.72-82
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• 2014

Recently, the size of semiconductor industry market is constantly growing, due to the increase in diffusion of smart-phone, tablet PC and SSD(Solid State Drive). Also, it is expected that the demand for TLC NAND-type flash memory would gradually increase, with the recent release of TLC NAND-type flash memory in the SSD market. There have been a lot of studies on SLC NAND flash memory, but no research on TLC NAND flash memory has been conducted, yet. Also, a test of NAND-type flash memory is depending on a high-priced external equipment. Therefore, this study aims to suggest a structure for an autonomous test with no high-priced external test device by modifying the existing SLC NAND flash memory and MLC NAND flash memory test algorithms and patterns and applying them to TLC NAND flash memory.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.61-64
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• 2003

Technological progress in integrated, low-power, CMOS communication devices and sensors makes a rich design space of networked sensors viable. These sensors can be deeply embedded in the physical world and spread throughout sensor network environment like smart dust. So ubiquitous computing will be come true. SmartDust project is the one of ubiquitous computing approach. It produces TinyOS, mote(mica, mica2, rene2, mica2dot, etc.), NesC, TinyDB, etc. We constructs sensor network test bed and tests to approach sensor network and ubiquitous computing.

• Proceedings of the KAIS Fall Conference
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• 2008.05a
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• pp.189-191
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• 2008

본 논문에서는 스캔 체인의 레이아웃 거리를 고려한 효율적인 Test Wrapper 설계 방식을 제안한다. SoC내의 스캔체인들을 테스트 하기 위해서는 외부 TAM line에 각 스캔체인들을 할당해야 한다. IP 내에 존재하는 스캔체인들은 스캔체인간 레이아웃 거리를 갖게 되며 이 거리가 클럭주기를 넘어가는 경우 체인의 타이밍 위반(Timing violation)이 발생될 수 있다. 본 논문에서는 타이밍 위반이 발생하지 않도록 체인간 거리를 고려하여 스캔체인을 할당하는 새로운 test wrapper 설계 방식을 제안하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.343-350
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• 2016

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connects (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 39K at an operating frequency of 313MHz using the $0.13{\mu}m$ TSMC process.

• The KIPS Transactions:PartA
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• v.14A no.7
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• pp.391-398
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• 2007

In this paper, we design a future mobile camera standard interface based on the MIPI CSI-2 and D-PHY specification. The proposed CSI-2 have the efficient multi-lane management layer, which the independent buffer on the each lane are merged into single buffer. This scheme can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. The proposed CSI-2 & D-PHY are verified under test bench. We make an experiment on CSI-2 & D-PHY with FPGA type test-bed and implement them onto a mobile handset. The proposed CSI-2 & D-PHY module are used as both the bridge type and the future camera processor IP for SoC.