• Journal of Internet Computing and Services
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• v.21 no.3
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• pp.11-19
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• 2020

In this paper, a merged TEA block cipher processor which unifies Tiny Encryption Algorithm(TEA), extended Tiny Encryption Algorithm(XTEA) and corrected block TEA(XXTEA) is designed. After TEA cipher algorithm was first designed, XTEA and XXTEA cipher algorithms were designed to correct security weakness. Three types of cipher algorithm uses a 128-bit master key. The designed cipher processor can encrypt or decrypt 64-bit message block for TEA/XTEA and variable-length message blocks up to 256-bit for XXTEA. The maximum throughput for 64-bit message blocks is 137Mbps and that of 256-bit message blocks is 369Mbps. The merged TEA block cipher designed in this paper has a 16% gain on the area side compared to a lightweight LEA cipher. The cryptographic IP of this paper is applicable in security module of the mobile areas such as smart card, internet banking, and e-commerce.

• The KIPS Transactions:PartC
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• v.17C no.5
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• pp.407-414
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• 2010

A condition access system (CAS) refers to a hardware-based system that allows only authenticated users to have access to contents. The CAS has many disadvantages found in that in the replacement of multiple service operator (MSO) a set-top box should be also changed and the smart-card often causes malfunction. To deal with the problems, exchangeable CAS (XCAS) was developed in 2009. However the standards or evaluation schemes for XCAS are absent. Existing evaluation schemes are not appropriate for evaluating XCAS due to the evaluation standard, the evaluation cost and efficiencies. Therefore, a specific scheme that can evaluate the security and suitability of exchangeable conditional access systems has been requested. In this paper, we propose an appropriate evaluation scheme for XCAS. The evaluation scheme includes an evaluation purpose and four components to evaluate the evaluation target, the evaluation process, the evaluation subject, and the evaluation cost involved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1510-1516
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• 2011

As emergence of the ubiquitous society, it is possible to access the network for services needed to us in anytime and anywhere. The phenomena has been accelerated by revitalization of the sensor network offering the sensing information and data. Currently, sensor network contributes the convenience for various services such as environment monitoring, health care and home automation. However, sensor network has a weak point compared to traditional network, which is easily exposed to attacker. For this reason, messages communicated over the sensor network, are encrypted with symmetric key and transmitted. A number of symmetric cryptography algorithms have been researched. Among of them HIGHT algorithm in hardware and software implementation are more efficient than tradition AES in terms of speed and chip size. Therefore, it is suitable to resource constrained devices including RFID tag, Sensor node and Smart card. In the paper, we present the optimized software implementation on the ultra-light symmetric cryptography algorithm, HIGHT.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.860-868
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• 2011

Feistel and SPN are the two main structures in a block cipher. Feistel is a symmetric structure which has the same structure in encryption and decryption, but SPN is not a symmetric structure. In this paper, we propose a SPN block cipher so called SSB which has a symmetric structure in encryption and decryption. The proposed SSB is composed of the even numbers of N rounds. Each round consists of a round key addition layer, a subsitution layer, a byte exchange layer and a diffusion layer. The subsitution layer of the odd round is inverse function of one of the even round. And the diffusion layer is a MDS involution matrix. The differential and linear attack probability of SSB is $2^{-306}$ which is same with AES. The proposed symmetric SPN block cipher SSB is believed to construct a safe and efficient cipher in Smart Card and RFID environments which is in limited hardware and software resources.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.778-784
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• 2012

A symmetric block cryptosystem uses an identical cryptographic key at encryption and decryption processes. HIGHT cipher algorithm is 64-bit block cryptographic technology for mobile device that was authorized as international standard by ISO/IEC on 2010. In this paper, block cipher HIGHT algorithm is designed using Verilog-HDL. Four modes of operation for block cipher such as ECB, CBC, OFB and CTR are supported. When continuous message blocks of fixed size are encrypted or decrypted, the desigend HIGHT core can process a 64-bit message block in every 34-clock cycle. The cryptographic processor designed in this paper operates at 144MHz on vertex chip of Xilinx, Inc. and the maximum throughput is 271Mbps. The designed cryptographic processor is applicable to security module of the areas such as PDA, smart card, internet banking and satellite broadcasting.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.10
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• pp.2750-2759
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• 2009

In this paper, we analyze vulnerabilities in a remote authentication protocol using smartcards which was proposed by Bindu et al. and propose an improved scheme. The proposed scheme can prevent from restricted replay attack and denial of service attack by replacing time stamp with random number. In addition, this protocol can guarantee user anonymity by transmitting encrypted user's ID using AES cipher algorithm. The computational load in our protocol is decreased by removing heavy exponentiation operations and user efficiency is enhanced due to addition of password change phase in which a user can freely change his password. Furthermore, we really implement the proposed authentication protocol using a STM smartcard and authentication server. Then we prove the correctness and effectiveness of the proposed remote authentication system.

• Proceedings of the Korean Information Science Society Conference
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• 2010.06a
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• pp.38-39
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• 2010

수도권 대중교통 이용자는 2004년 서울시의 대중교통 체계 개편에 따라 교통 카드를 사용하여 버스와 지하철을 이용하게 되었다. 교통 카드를 사용하는 각 승객의 승차와 하차에 관한 데이터가 하나의 트랜잭션으로 구성되고, 하루 천만 건 이상의 트랜잭션들로 구성된 대용량 교통카드 트랜잭션 데이터베이스가 만들어지고 있다. 대중교통을 이용하는 승객들의 승차와 하차에 관한 여러 정보를 담고 있는 교통카드 트랜잭션 데이터베이스에서 유용한 패턴이나 정보를 탐사해내는 연구가 계속 진행되고 있다. 이런 연구 결과는 수도권 대중교통 정책을 입안하는데 중요한 기초 자료가 되고 수도권 승객들에게 대중교통을 보다 잘 이용할 수 있는 정보로 제공된다. 교통카드 이용률은 2006년 79.5%, 2007년 80.3%, 2008년 81.6%로 점차적으로 증가하고 있다. 대용량의 교통카드 트랜잭션 데이터베이스에 대한 연구를 살펴보면 하루 동안의 교통카드 트랜잭션 데이터베이스에서 순차 패턴을 탐사하는 알고리즘을 연구하였고[1], 승객들의 통행 패턴에 대한 분석연구를 확장하여 일 년에 하루씩 2004년에서 2006년까지 3일간의 교통카드 트랜잭션 데이터베이스로부터 승객 시퀀스의 평균 정류장 개수와 환승 횟수 등을 연도별로 비교하였다[2]. 수도권 지하철 시스템의 특성에 관한 연구로는 네트워크 구조 분석이 있었고[3], 승객의 기종점 통행 행렬(Origin-Destination trip matrix)에 의한 승객 흐름의 분포가 멱함수 법칙(power law)임을 보여주는 연구가 있었고[4], 지하철 교통망에서 모든 링크상의 승객들의 흐름을 찾아내는 연구가 있었다[5]. 본 논문에서는 교통카드 트랜잭션 데이터베이스에서 지하철 승객들의 통근 패턴을 탐사해내는 방법을 연구하였다. 수도권 지하철 네트워크에 대한 정보를 입력하고 하루치의 교통카드 트랜잭션 데이터베이스에 연구된 방법을 적용하여 8가지 통근 패턴들을 탐사해내고 분석하였다. 탐사된 패턴들 중에서 많은 승객들이 지지하는 출퇴근 패턴에 대해서는 시간대별로 승객수를 그래프로 보여주었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.786-792
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• 2016

Camellia was jointly developed by Nippon Telegraph and Telephone Corporation and Mitsubishi Electric Corporation in 2000. Camellia specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, a modified round operation block which unifies a register setting for key schedule and a conventional round operation block is proposed. 16 ROMs needed for key generation and round operation are implemented using only 4 dual-port ROMs. Due to the use of a message buffer, encryption/decryption can be executed without a waiting time immediately after KA and KB are calculated. The suggested block cipher Camellia algorithm is designed using Verilog-HDL, implemented on Virtex4 device and operates at 184.898MHz. The designed cryptographic core has a maximum throughput of 1.183Gbps in 128-bit key mode and that of 876.5Mbps in 192 and 256-bit key modes. The cryptographic core of this paper is applicable to security module of the areas such as smart card, internet banking, e-commerce and satellite broadcasting.

• Journal of Digital Convergence
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• v.15 no.10
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• pp.253-260
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• 2017

Authenticated key agreement in multi-server environments is one of very important security issues because only authorized user needs to access their data and services. To support this issue, numerous schemes have been proposed over recent years. Recently, Shin showed the security weaknesses in the previous scheme and proposed an improved scheme called SIAKAS to solve them. Unfortunately, this paper shows that SIAKAS is still weak against application server impersonation attack and could be traceable to attackers. To solve the problems in SIAKAS, we propose an untraceable authenticated key agreement scheme, denoted by UAKAS. UAKAS efficiently solves security and privacy issues in SIAKAS and the related schemes and could reduce the operation overhead at least 12% compared to them.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.8-15
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• 2007

This paper proposed hardware architecture of the block cryptographic algorithm HIGHT aiming small size and low power application, and analyzed its performance. The HIGHT is a modified algorithm of the Feistel. The encryption and decryption circuit were designed as one iterative block. It reduces the redundant circuit that yields small area. For the performance improvement, the circuit generates 32-bit subkey during 1 clock cycle. we synthesized the HIGHT with Hynix $0.25-{\mu}m$ CMOS technology. The proposed circuit size was 2.658 EG(equivalent gate), and its power consumption was $10.88{\mu}W$ at 2.5V for 100kHz. It is useful for a passive RFID tag or a smart IC card of a small size and low power.