• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2192-2195
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• 2003

This parer proposes a power-line phase measurement algorithm which is based on the recursive implementation of sliding-DFT. Usage of the single DFT coefficient in the conventional sliding-DFT based power-line phase measurement brings a significant error propagation when implemented in hardware with finite word-length arithmetic operations. The proposed algorithm utilizes all the N-point DFT coefficients in the recursion. Performance degradation caused by the finite word- length implementation of the algorithm is analyzed and verified with computer simulations. The robustness of the proposed phase measurement algorithm against the erroneous implementation is also confirmed by the performance analysis and simulation.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.12
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• pp.584-589
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• 2001

This paper presents an implementation method of multi-channel synchronized phasor measurement device, which is based on the ASIC implementation of the sliding-DFT. A time-shared multiplier structure is proposed to minimize the number of gates required for the implementation. The design is verified by the timing simulation of its operation. The effect of coefficient approximation in the recursive implementation of the sliding-DFT is analytically derived and verified with the computer simulations.

• The Journal of the Acoustical Society of Korea
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• v.18 no.8
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• pp.48-53
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• 1999

This paper presents an analytic derivation of the erroneous effect when the sliding-DFT is implemented in a recursive way with the finite-bit approximation of the twiddle factors. The analysis result is obtained in a closed form equation of the noise-to-signal power ratio(NSR) employing the zero-mean white Gaussian signal as the target input of the DFT. The parameters of the wordlength used in representing the twiddle factors and the blocklength of the DFT appear in the NSR explicitly as its function variables. The derivation is based on the error dynamic equation which is derived from the recursive SDFT, and on the analytic exploration of the statistical characteristics of the approximation coefficients treating them as random variables of having spatial distributions. The analytically derived results are verified through the comparison with the data actually measured from the computer simulation experiment.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.4
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• pp.470-476
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• 2002

This paper presents an analysis of the performance degradation of coefficient approximation and frequency deviation in phase measurement algorithm based on Sliding-DFT. The analytic derivation is based on the statistics of the error dynamic equation that describes the error propagation of the recursion. The analysis result is intended to obtain a closed-form equation of error variance in terms of the number of bits used in coefficient approximation, the length of the DFT data block, and noise. It is verified with data obtained from the computer simulations.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.128-135
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• 2004

This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. The size of phase error caused by the finite wordlength implementation of DFT twiddle factors is shown significantly lower than that of magnitude error. The drastic reduction of the phase error is achieved by the exploitation of the quadruplet symmetry characteristics of the approximated twiddle factors in the complex plane. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The operation of the developed system is also verified by the experiment performed under the test environment implemented with the multi-channel function generator and the on-line interfaced host processor system. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2678-2680
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• 2003

본 논문에서는 sliding-DFT의 순환구현을 기반한 실시간 위상 측정 앨고리즘을 제시하였다. 종래의 순환형 SDFT 기반 위상 측정 기법은 단일 계수를 사용하기 때문에 계수 근사가 적용되는 하드웨어 구현시 심각한 오차 파급 특성을 나타낸다. 본 논문에서는 순환 구조이면서 회전 위상을 보정을 통해 N-point DFT의 N개의 모든 계수를 적용한 위상 측정 기법을 제시하였고, FPGA 등 하드웨어 구현에 있어서 계수의 유한 비트 근사에 따르는 성능 열화를 해석하였다. 제안한 위상측정 앨고리즘은 실시간 다채널 위상 측정이 가능하도록 FPGA에 구현하였고 동작을 확인하였다.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.143-146
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• 2001

본 논문에서는 다 채널 페이저 연산 장치를 전용하드웨어로 구현하기 위한 설계 구조에 대하여 제시하였으며, 이를 연산량이 많은 곱셈기를 시분할에 의해 공유하는 구조를 제시하였다. 또한 페이저 측정을 위한 Sliding-DFT 알고리즘을 순환 구현할 경우의 근사구현 오차에 관한 정량적인 연구를 수행하였다. 이러한 오차 영향의 해석을 기반으로 하여 곱셈기 공유 구조를 적용한 페이저 연산 장치를 설계하고, 설계한 하드웨어의 내부동작을 보여주는 시뮬레이션을 통해 설계의 정확성을 확인하였다

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.4
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• pp.305-313
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• 2013

As an FMT (Filtered Multi-Tone) transmission method of Wideband VHF communication system specified by the ETS (European Telecommunications Standards) EN 300 392-2, this paper introduces three existing realization methods, i.e., the direct filtering method using different band SRRC (Square-Root Raised Cosine) filters for each subcarrier, the PPN-DFT method using the IDFT-PPN (Poly-Phase Network) and PPN-DFT at the transmitter and receiver, respectively, and the Extended DFT method. Then, it proposes the extended IDFT-SDFT (Sliding Discrete Fourier Transform) that computes the DFT values only for interested subcarriers every sample time, and shows that it has an advantage of blind symbol timing (using no training symbol) individually for each user signal (independently of other users' signals) in the multi-user environment where the subcarriers are assigned in contiguous or interleaved blocks to each user and each user signal possibly experiences different channels.

• Journal of Electrical Engineering and Technology
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• v.7 no.6
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• pp.1014-1022
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• 2012

This paper proposes a modified recursive sliding DFT to measure the phase of a single-tone. The modification is to provide a self error-cancelling mechanism so that it can significantly reduce the numerical error, which is generally introduced and accumulated when a recursive algorithm is implemented in finite wordlength arithmetic. The phase measurement error is analytically derived to suggest optimized distributions of quantization bits. The analytic derivation and the robustness of the algorithm are also verified by computer simulations. It shows that the maximum phase error of less than $5{\times}10^{-2}$ radian is obtained even when the algorithm is coarsely implemented with 4-bit wordlength twiddle factors.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.3
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• pp.191-193
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• 2005

This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The proposed algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.