• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.7
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• pp.657-663
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• 2009

A fully integrated single ended IR-UWB receiver is implemented using 0.18 ${\mu}m$ CMOS technology. The UWB receiver adopts the non-coherent architecture, which simplifies the RF architecture and reduces power consumption. The receiver consists of single-ended 2-stage LNAs, S2D, envelope detector, VGA, and comparator. The measured results show that sensitivity is -80.8 dBm at 1 Mbps and BER of $10^{-3}$. The receiver uses no external balun and the chip size is only $1.8{\times}0.9$ mm. The consumed current is very low with 13 mA at 1.8 V supply and the energy per bit performance is 23.4 nJ/bit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.248-252
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• 2001

A noble single-ended input, double-balanced mixer topology is proposed. The mixer incorporates the common-source amplifier input stage with inductive degeneration for impedance matching. The analysis based on simulations shows that the overall performance of the mixer is excellent and is adjustable by varying the input transistor size to give best characteristics for the given linearity specifications.

• Journal of Korea Multimedia Society
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• v.16 no.1
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• pp.50-55
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• 2013

This article presents a simple and reasonable in-service, real-time, and continuous single-ended objective video quality assessment model for DTV broadcasting using a multiburst signal at the bottom of the transient effect area, similar to Vertical Interval Test Signals. The issue of in-service video-quality monitoring in DTV broadcasting is addressed, and an effective method of quality monitoring is presented. The proposed method is also implemented and tested in a range of situations using a simulated HDTV broadcasting network.

• Journal of IKEEE
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• v.24 no.3
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• pp.719-726
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• 2020

A threshold-voltage sensing circuit is proposed to compensate for pixel aging in active matrix organic light-emitting diodes. The proposed threshold-voltage sensing circuit consists of sample-hold (S/H) circuits and a single-ended successive approximation register (SAR) analog-to-digital converter (ADC) with a resolution of 10 bits. To remove a scale down converter of each S/H circuit and a voltage gain amplifier with a signl-to-differentail converter, the middle reference voltage calibration and input range calibration for the single-ended SAR ADC are performed in the capacitor digital-to-analog converter and reference driver. The proposed threshold-voltage sensing circuit is designed by using a 180-nm CMOS process with a supply voltage of 1.8 V. The ENOB and power consimption of the single-ended SAR ADC are 9.425 bit and 2.83 mW, respectively.

• Journal of Power Electronics
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• v.19 no.2
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• pp.403-412
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• 2019

Aiming at the problems of large dv/dt and di/dt in traditional single-ended converters and high electromagnetic interference (EMI) noise levels, a single-ended isolated converter using the secondary resonance technique is proposed in this paper. In the proposed converter, the voltage stress of the main power switch can be reduced and the voltage across the output diode is clamped to the output voltage when compared to the conventional flyback converter. In addition, the peak current stress through the main power switch can be decreased and zero current switching (ZCS) of the output diode can be achieved through the resonance technique. Moreover, the EMI noise coupling path and an equivalent model of the proposed converter topology are presented through the operational principle of the proposed converter. Analysis results indicate that the common mode (CM) EMI noise and the differential mode (DM) EMI noise of such a converter are deduced since the frequency spectra of the equivalent controlled voltage sources and controlled current source are decreased when compared with the traditional flyback converter. Furthermore, appropriate parameter selection of the resonant circuit network can increase the equivalent impedance in the EMI coupling path in the low frequency range, which further reduces the common mode interference. Finally, a simulation model and a 60W experimental prototype of the proposed converter are built and tested. Experimental results verify the theoretical analysis.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1468-1479
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• 2015

Renewable energy resources such as wind and photovoltaic power generation systems demand a high step-up DC-DC converters to convert the low voltage to commercial grid voltage. However, the high step-up converter using a transformer has limitations of high voltage stresses of switches and diodes when the transformer winding ratio increases. Accordingly, conventional studies have been applied to series-connect multioutput converters such as forward-flyback and switched-capacitor flyback to reduce the transformer winding ratio. This paper proposes new single-ended converter topologies of an isolation type and a non-isolation type to improve power efficiency, cost-effectiveness, and output ripple. The first proposal is an isolation-type charge-pump switched-capacitor flyback converter that includes an extreme-ratio isolation switched-capacitor cell with a chargepump circuit. It reduces the transformer winding number and the output ripple, and further improves power efficiency without any cost increase. The next proposal is a non-isolation charge-pump switched-capacitor-flyback tapped-inductor boost converter, which adds a charge-pump-connected flyback circuit to the conventional switched-capacitor boost converter to improve the power efficiency and to reduce the efficiency degradation from the input variation. In this paper, the operation principle of the proposed scheme is presented with the experimental results of the 100 W DC-DC converter for verification.

• Journal of IKEEE
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• v.23 no.3
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• pp.1046-1053
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• 2019

In a multi-channel single-ended system, the far-end crosstalk (FEXT) due to mutual inductance and mutual capacitance between two adjacent channels critically limit the bandwidth. FEXT causes crosstalk-induced jitter (CIJ) and crosstalk-induced glitch (CIG) which leads to timing margin and voltage margin degradations, respectively. Therefore, FEXT must be compensated in order to increase eye opening and achieve high data-rate. It can be compensated in transmitter by controlling the timing of the data or reshaping the waveform of the signal. Also, FEXT can be compensated in receiver by generating mimicked FEXT using high-pass filter. In this paper, recent techniques to compensate FEXT are investigated, with discussions of their pros and cons.

• ETRI Journal
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• v.33 no.2
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• pp.291-294
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• 2011

This letter proposes an open-ended waveguide antenna with a single split-ring resonator. In contrast to the waveguide antennas incorporating multiple rings reported in a previous study, which exhibited narrow bandwidth, the proposed antenna uses only one ring to achieve broader bandwidth while keeping the aperture small. A single ring has a relatively low quality factor compared to multiple rings. The simulated and measured fractional bandwidth was 4.13% and 4.03%, respectively, which is much broader than the fractional bandwidth of about 1% demonstrated in a previous study. This simple technique can be used in many applications that require small apertures including near-field probes and array elements.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.95-96
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• 2015

In this paper, a single-sourced PV PCS using the trinary asymmetric MLI with a single-ended pre-regulator is proposed. Trinary based asymmetric CHB inverters provide higher output levels for the same number of cells compared to other CHB inverters. However, there is an issue of regeneration with trinary asymmetric inverters and this complicates the system with requirement of bi-directional converters at the input. Modified commutation strategies have been used to remove the regeneration issue with compromise in THD. The single-ended pre-regulator provides the isolated dc-link voltage for the individual H-bridge cells with the advantage of having a single switch and magnetic component. This implementation increases the magnetic utilization of the inductor core and reduces the switching loss in the pre-regulator and also the reduced parts count contributes to the cost competiveness of the proposed PCS. The proposed PV PCS has been verified using simulation results in this paper.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.719-726
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• 2008

In this paper, we designed driving IC for 500 V resonant half-bridge type power converter, In this single-ended level shifter, chip area and power dissipation was decreased by 50% and 23.5% each compared to the conventional dual-ended level shifter. Also, this newly designed circuit solved the biggest problem of conventional flip-flop type level shifter in which the power MOSFET were turned on simultaneously due to the large dv/dt noise. The proposed high side level shifter included switching noise protection circuit and schmmit trigger to minimize the effect of displacement current flowing through LDMOS of level shifter when power MOSFET is operating. The designing process was proved reasonable by conducting Spectre and PSpice simulation on this circuit using 1${\mu}m$ BCD process parameter.