• 전자공학회지
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• 제29권3호
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• pp.36-40
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• 2002

• 대한기계학회논문집A
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• 제28권6호
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• pp.774-782
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• 2004

This article presents a numerical and experimental investigation for the single-phase forced laminar convective heat transfer through arrays of micro-channels in micro heat exchangers to be used for cooling power-intensive semiconductor packages, especially the stacked multi-chip modules. In the numerical analysis, a parametric study was carried out for the parameters affecting the efficiency of heat transfer in the flow of coolants through parallel rectangular micro-channels. In the experimental study, the cooling performance of the micro heat exchanger was tested on prototypes of stacked multi-chip modules with difference channel dimensions. The simulation results and the experiment data were acceptably accordant within a wide range of design variations, suggesting the numerical procedure as a useful method for designing the cooling mechanism in stacked multi-chip packages and similar electronic applications.

• 전자공학회논문지
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• 제50권3호
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• pp.42-49
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• 2013

본 논문에서는 동시에 양방향 통신이 가능한 inductively-coupled link를 제안하고자 한다. 기존의 inductively-coupled link의 경우 채널을 통해 양방향 데이터 전송이 가능하지만 동시에 양방향으로 데이터 전송은 불가능하였다. Echo를 효과적으로 제거함으로써 동시에 양방향 통신이 가능하게 하였고 데이터 전송률 또한 높일 수 있었다. 동시에 양방향 통신 구조에서 각각의 chip은 송신과 수신을 동시에 수행한다. 테스트를 위해 3차원으로 chip을 적층하는 대신 하나의 chip 내에서 유사한 테스트 환경을 구현하였으며 $0.13-{\mu}m$ CMOS 공정을 이용하여 제작 되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 B
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.

• 한국전기전자재료학회논문지
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• 제37권5호
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• pp.527-532
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• 2024

Physically Unclonable Functions (PUFs) provide a high level of security for private keys using unique physical characteristics of hardware. However, fabricating PUF chips requires numerous semiconductor processes, leading to high costs, which limits their applications. In this work, we introduce a low-cost manufacturing method for PUF security chips. First, surface roughening through wet-etching is utilized to create random variables. Additionally, physical vapor deposition is added to further enhance randomness. After PUF chip fabrication, both Hamming distance (HD) and Hamming weight (HW) are extracted and compared to verify the fabricated chip. It is confirmed that the PUF chip using two different multiple process variables demonstrates superior uniqueness and uniformity compared to the PUF security chip fabricated using only a single process variable.

• 전자공학회논문지B
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• 제31B권7호
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.497-500
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• 2005

This paper presents a design of a hybrid sensor chip which integrates an A/D converter module and a phase measurement module for measuring power line phase. Recursive sliding DFT based phase measurement module is designed using time shared multiplier which can reduce the size of SoC implementation. A/D converter is based on the sigma delta modulation in order to minimize the implementation space of the analog part and designed to obtain 8-bit resolution. Computer simulations and FPGA implementation are performed to verify hybrid sensor chip design. The hybrid sensor chip for 4-channel power line phase measurement is fabricated by using 0.35 micrometer CMOS process.

• 전자공학회논문지C
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• 제34C권4호
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• pp.1-15
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• 1997

This paper proposes CMOS on-chip voltage and current reference circuits that operate at supply voltages between 2.5V and 5.5V without using a vonventional bandgap voltage structure. The proposed reference circuits based on enhancement-type MOS transistors show low cost, compatibility with other on-chip MOS circuits, low-power consumption, and small-chip size. The prototype was implemented in a 0.6 um n-well single-poly double-metal CMOS process and occupies an active die area of $710 um \times 190 um$. The proposed voltage reference realizes a mean value of 0.97 V with a standard deviation of $\pm0.39 mV$, and a temperature coefficient of $8.2 ppm/^{\circ}C$ over an extended temeprature range from TEX>$-25^{\circ}C$ to $75^{\circ}C$. A measured PSRR (power supply rejection ratio) is about -67 dB at 50kHz.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2001년도 춘계학술대회 논문집(한국공작기계학회)
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• pp.101-106
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• 2001

In order to establish the optimum process parameters and diamond saw blade composition for machining natural stone, the chip formation process and the wear process must be understood. Diamond saw blade is one of the most effective, versatile, and extensively used methods of processing rock and other hard materials, such as granite, marble, concrete and asphalt. For many years, it has been known that chip thickness is one of the most significant in the understanding of the sawing process, and other variables such as force and power have been correlated with it. In this study, mathematical relations of a material chipped by a single grit of the saw blade will be undertaken. The material chipping geometries have been mathematically defined and derived as maximum chip thickness.

• 제어로봇시스템학회논문지
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• 제6권9호
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• pp.836-843
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• 2000

A sequence planning method is proposed to reduce the assembly time of gantey-type chip mounters with single head. The overall path of the chip mounter is divided into forward and backward path, and formulate the optimization problem is formulated as an transpoetation problem and an Euler's tour problem. The transportation alforithm is applied to find optimal backward path, and Euler's tour algorithm used to generate an assembly sequence. Simulation results are presented to verify the usefulness of the proposed method.