• Journal of the Institute of Electronics Engineers of Korea SD
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• 제47권1호
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• pp.94-101
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• 2010

Optimization of interconnects among processors and memories becomes important as multiple processors and memories can be integrated on a Multi-Processor System-on-Chip (MPSoC). Since the optimal interconnection architecture is usually dependent on the applications, systematic design methodology for various data transfer requirements is necessary. In this paper, we focus on bus interconnection for MPSoC applications which use 4 ~ 16 processors. We propose a new systematic bus design methodology under performance constraints using Single Arbitration Multiple Bus Accesses (SAMBA) style bus architectures. Optimized bus architecture is found to satisfy performance constraints for a single or multiple applications. When compared to the unoptimized architecture, our method can reduce the bus switch logic circuits significantly (by more than 50% sometimes). Furthermore, low cost bus architectures can be found to satisfy the performance constraints for multiple applications.

• Proceedings of the KIEE Conference
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• 대한전기학회 2006년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.125-128
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• 2006

This paper presents a novel type soft switching PWM power frequency AC-AC converter using bidirectional active switches or single phase utility frequency AC-high frequency AC matrix converter. This converter can directly convert utility frequency AC (UFAC, 50Hz/60Hz) power to high frequency AC (HFAC) power ranging more than 20kHz up to 100kHz. A novel soft switching PWM prototype of high frequency multi-resonant PWM controlled UFAC-HFAC matrix converter using antiparallel one-chip reverse blocking IGBTs manufactured by IXYS corp. is based on the soft switching resonance with asymmetrical duty cycle PWM strategy. This single phase UFAC-HFAC matrix converter has some remarkable features as electrolytic capacitor DC busline linkless topology, unity power factor correction and sine-wave line current shaping, simple configuration with minimum circuit components, high efficiency and downsizing. This series load resonant UFAC-HFAC matrix converter, incorporating bidirectional active power switches is developed and implemented for high efficiency consumer induction heated food cooking appliances in home uses and business-uses. Its operating performances as soft switching operating ranges and high frequency effective power regulation characteristics are illustrated and discussed on the basis of simulation and experimental results.

• Journal of the Korea Academia-Industrial cooperation Society
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• 제12권1호
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• pp.357-363
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• 2011

This paper presents a simple LCD CCFL-backlight resonant inverter. First, in introduction various conventional inverter topologies for the CCFL are reviewed, briefly, and then, in each main subject the proposed inverter is explained, in detail. The proposed inverter utilizes a new class-E resonant circuit with a single-switch and is controlled by a single-chip microcontroller, which is very simple. Moreover, the proposed inverter can ensure resonant zero voltage switching (ZVS) under most operating conditions and performs simply the digital dimming control. It is shown through experimental results that the proposed inverter has good performance for the LCD CCFL-backlight.

• Progress in Superconductivity
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• 제4권1호
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• pp.74-79
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• 2002

High-speed probe made to test single flux quantum(SFQ) circuits was comprised of semi-rigid coaxial cables and microstrip lines. The impedance was set at 50 $\Omega$to carry high-speed signals without much loss. To do performance test of high-speed probe, we have attempted to fabricate a test chip which has a coplanar waveguide(CPW) structure. Electromagnetic simulation was done to optimize the dimension of CPW so that the CPW structure has an impedance of 50$\Omega$, matching in impedance with the probe. We also used the simulation to investigate the effect of the width of signal line and the gap between signal line and ground plane to the characteristics of CPW structure. We fabricated the CPW structure with a gold film deposited on Si wafer whose resistivity was above $1.5\times$10$_4$$\Omega$.cm. The magnitudes of S／sub 21／ of CPW at 6 ㎓ in simulations and in the actual measurements done with a network analyzer were: -0.1 ㏈ and -0.33 ㏈ (type A),-0.2 ㏈ and -0.48 ㏈ (type B), respectively. Using the test chip, we have successfully tested the performance of high-speed probe made for SFQ circuits. The probe showed the good performance overthe bandwidth of 10 ㎓.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제41권10호
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• pp.23-29
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• 2004

In this paper, the asynchronous quasi dual-port SRAM employing a single port structure in SRAM embedded SOC (System On Chip) is proposed. External host can access the internal SRAM freely and the data on internal SRAM can be transferred to an another external circuitry without a synchronous signal of an external host, which operates as an asynchronous dual-port SRRAH The performances of the proposed circuits and control structure are verified through the simulation and we fabricated it using a 0.35um CMOS technology. As the results, the chip shows reduced area about 20% and saved power also 20% than conventional architectures.

• Biotechnology and Bioprocess Engineering:BBE
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• 제11권2호
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• pp.146-153
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• 2006

A passive microfluidic delivery system using hydrophobic valving and pneumatic control was devised for microfluidic handling on a chip. The microfluidic metering, cutting, transport, and merging of two liquids on the chip were correctly performed. The error range of the accuracy of microfluid metering was below 4% on a 20 nL scale, which showed that microfluid was easily manipulated with the desired volume on a chip. For a study of the feasibility of biochemical reactions on the chip, a single enzymatic reaction, such as ${\beta}-galactosidase$ reaction, was performed. The detection limit of the substrate, i.e. fluorescein $di-{\beta}-galactopyranoside$ (FDG) of the ${\beta}-galactosidase$ (6.7 fM), was about 76 pM. Additionally, multiple biochemical reactions such as in vitro protein synthesis of enhanced green fluorescence protein (EGFP) were successfully demonstrated at the nanoliter scale, which suggests that our microfluidic chip can be applied not only to miniaturization of various biochemical reactions, but also to development of the microfluidic biochemical reaction system requiring a precise nano-scale control.

• Proceedings of the KIEE Conference
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• 대한전기학회 2004년도 하계학술대회 논문집 C
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• pp.2128-2130
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• 2004

High throughput analysis using a DNA chip microarray is powerful tool in the post genome era. Less labor-intensive and lower cost-performance is required. Thus, this paper aims to develop the multi-channel type label-free DNA chip and detect SNP (Single nucleotide polymorphisms). At first, we fabricated a high integrated type DNA chip array by lithography technology. Various probe DNAs were immobilized on the microelectrode array. We succeeded to discriminate of DNA hybridization between target DNA and mismatched DNA on microarray after immobilization of a various probe DNA and hybridization of label-free target DNA on the electrodes simultaneously. This method is based on redox of an electrochemical ligand.

• Journal of Institute of Control, Robotics and Systems
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• 제10권3호
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• pp.261-266
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• 2004

Recently, a variety of intelligent robots are developed for the personal purpose beyond the industrial application. These intelligent robots have ranges of sensors, actuators, and control algorithms to their application. In this paper we propose a reconfigurable robot controller, $SR^2$c (The SOPC-based Reconfigurable Robot Controller), based on SOPC (System on a Programmable Chip), that can be reconfigurable easily by software. The proposed robot controller contains not only a processing module but also robot-specific IP's. To show a feasibility of the proposed robot controller, a small entertainment robot, Wizard-4 is implemented with a single chip controller as proposed in this paper.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.869-872
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• 2005

In this paper we present a switch wrapper for an AMBA AXI, which is an efficient on-chip-network interface compared to bus-based interfaces in a multiprocessor SoC. The AXI uses an idea of NoC to provide the increasing demands on communication bandwidth within a single chip. A switch wrapper for AXI is located between a interconnection network and two IPs connecting them together. It carries out a mode of routing to interconnection network and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, AHB-AXI converters, interface modules and a controller modules. We propose the design of a all-in-one type switch wrapper.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.893-896
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• 2005

This paper describes Low Noise Amplifier(LNA) and Single Balanced Mixer(SBM) with monolithic image rejection notch filter using 0.5um MESFET process. LNA, Notch filter, and SBM were integrated on a chip. This chip does not need off chip SAW filter, thereby reducing the overall cost and system volume. The LNA with Notch filter provides a gain of 15dB, noise figure of 1.2dB, and image rejection ratio of -74dB. The SBM has a conversion gain of 6dB.