• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.143-151
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• 2010

In this work, we propose a single electron memory 'SEM' design which consist of two key blocs: A memory bloc, with a voltage source $V_{Mem}$, a pure capacitor connected to a tunnel junction through a metallic memory node coupled to the second bloc which is a Single Electron Transistor "SET" through a coupling capacitance. The "SET" detects the potential variation of the memory node by the injection of electrons one by one in which the drainsource current is presented during the memory charge and discharge phases. We verify the design of the SET/SEM cell by the SIMON tool. Finally, we have developed a MAPLE code to predict the retention time and nonvolatility of various SEM structures with a wide operating temperature range.

• ETRI Journal
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• 제35권5호
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• pp.808-818
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• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

• 한국전자통신학회논문지
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• 제7권5호
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• pp.1061-1066
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• 2012

디지털 메모리는 신뢰성, 속도 그리고 상대적인 단순한 제어회로로 인해 지금까지 저장장치로서 널리 사용되어 왔다. 그러나 디지털 메모리 저장능력은 공정의 선폭감소의 한계로 인해 결국 한계에 다다르게 될 것이다. 이러한 저장 능력을 획기적으로 증가시키는 방안의 하나로서 메모리의 셀에 저장하는 데이터의 형태를 디지털에서 아날로그로 변화시키는 것이다. 한 개의 셀과 프로그래밍을 위한 주변회로로 구성된 아날로그 메모리가 0.16um 표준 CMOS 공정에서 제작되었다. 제작된 아날로그 메모리는 저밀도 불활성 메모리, SRAM과 DRAM에서 리던던시 회로 제어, ID나 보안코드 레지스터, 영상이나 음성 저장장치 등에 응용될 것이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• ETRI Journal
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• 제29권1호
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• pp.124-126
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• 2007

In this letter, we study the impact of single event upsets (SEUs) in space or defense electronic systems which use memory devices such as EEPROM, and SRAM. We built a microcontroller test board to measure the effects of protons on electronic devices at various radiation levels. We tested radiation hardening at beam current, and energy levels, measured the phenomenon of SEUs, and addressed possible reasons for SEUs.

• 한국컴퓨터정보학회논문지
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• 제21권4호
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• pp.1-8
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• 2016

In small embedded systems including IoT devices, memory size is very small and it is important to reduce memory amount for execution of application programs. For multi-threaded applications, stack may consume a large amount of memory because each thread has its own stack of sufficiently large size for worst case. This paper presents an implementation of single stack multi-threading, called SSThread (Single Stack Thread), by sharing a stack for all threads to reduce stack memory size. By using SSThread, multi-threaded applications can be programmed based on normal C language environment and there is no requirement of transporting multi-threading operating systems. It consists of several library functions and various C macro definitions. Even though some functional restrictions in comparison to operating systems supporting complete multi-thread functionalities, it is very useful for small embedded systems with tiny memory size and it is simple to setup programming environment for multi-thread applications.

• 제어로봇시스템학회논문지
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• 제13권6호
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• pp.519-524
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• 2007

The OBC(on-board computer) of a satellite which plays a role of the controller for the satellite should be equipped with preventive measures against transient errors caused by SEU(single event upset). Since memory devices are pretty much susceptible to these transient errors, it is essential to protect memory devices against SFU. A common method exploits an error detection and correction code and additional memory devices, combined with periodic memory scrubbing. This paper proposes an effective memory scrubbing scheme for the OBC of STSAT-2. The memory system of the OBC is briefly mentioned and the reliability of the information stored in the memory system is analyzed. The result of the reliability analysis shows that there exist optimal scrubbing periods achieving the maximum reliability for allowed overall scrubbing overhead and they are dependent on the significance of the information stored. These optimal scrubbing periods from a reliability point of view are derived analytically.

• 마이크로전자및패키징학회지
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• 제19권4호
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권6호
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• pp.425-432
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• 2004

In this paper, we introduce the analog memory fabricated in a 0.35${\mu}{\textrm}{m}$ single poly standard CMOS process. We measured the programming characteristics of the analog memory cell such as linearity, reliability etc. Finally, we found that the characteristics of the programming of the cell depend on the magnitude and the width of the programming pulse, and that the accuracy of the programming within 10mV is feasible under the optimal condition. In order to standardize the characteristics of the cell, we have investigated numbers of cells. Thus we have used a program named Labview and a data acquisition board to accumulate the data related to the programming characteristics automatically.

• 대한전자공학회논문지TC
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• 제45권10호
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• pp.10-16
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• 2008

보통 저궤도를 선회하는 위성은 자기장으로 연결된 반알렌대를 통과하며, 이 안에 갇혀 주기적인 운동으로 남극과 북극을 이동하는 하전입자에 의해 부품이 손상되고 수명이 단축되는 악 영향을 받고 있다. 그중 방사선에 의한 SEU (Single Event Upset) 등은 우주선에 탑재된 반도체 소자의 오동작 유발의 원인이 되고 있다. 본 연구에서는 우주환경 방사선에서 고려해야 할 점들 중에서 특히 과학기술위성 1호 탑재 컴퓨터(On-board Computer, OBC)에서의 싱글이벤트업셋(Single Event Upset, SEU)의 영향을 고찰해 보고 거기에서 극복할 수 있는 알고리즘을 제시하고 있다. SEU 누적을 방지하기 위하여 매 일정한 시간마다 전체 메모리를 읽고/쓰는 과정(memory wash)이 필요하며 워쉬 주기 선정에 대해서도 고찰했다. 이러한 실험은 과학기술위성 시리즈 및 저궤도 위성용 탑재 컴퓨터의 성능 저하를 이해하는데 도움을 줄 수 있을 뿐만 아니라, 다목적 실용위성 시리즈의 각 모듈 개발에도 적극 활용 할 수 있을 것으로 기대된다.