• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.143-151
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• 2010

In this work, we propose a single electron memory 'SEM' design which consist of two key blocs: A memory bloc, with a voltage source $V_{Mem}$, a pure capacitor connected to a tunnel junction through a metallic memory node coupled to the second bloc which is a Single Electron Transistor "SET" through a coupling capacitance. The "SET" detects the potential variation of the memory node by the injection of electrons one by one in which the drainsource current is presented during the memory charge and discharge phases. We verify the design of the SET/SEM cell by the SIMON tool. Finally, we have developed a MAPLE code to predict the retention time and nonvolatility of various SEM structures with a wide operating temperature range.

• ETRI Journal
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• v.35 no.5
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• pp.808-818
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• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.5
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• pp.1061-1066
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• 2012

A digital memory has been widely used as a device for storing information due to its reliable, fast and relatively simple control circuit. However, the storage of the digital memory will be limited by the inablility to make smaller linewidths. One way to dramatically increase the storeage capability of the memory is to change the type of stored data from digital to analog. The analog memory fabricated in a standard single poly 0.6um CMOS process has been developed. Single cell and adjacent circuit block for programming have been designed and characterized. Applications include low-density non-volatile memory, control of redundancy in SRAM and DRAM memories, ID or security code registers, and image and sound memory.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• ETRI Journal
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• v.29 no.1
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• pp.124-126
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• 2007

In this letter, we study the impact of single event upsets (SEUs) in space or defense electronic systems which use memory devices such as EEPROM, and SRAM. We built a microcontroller test board to measure the effects of protons on electronic devices at various radiation levels. We tested radiation hardening at beam current, and energy levels, measured the phenomenon of SEUs, and addressed possible reasons for SEUs.

• Journal of the Korea Society of Computer and Information
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• v.21 no.4
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• pp.1-8
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• 2016

In small embedded systems including IoT devices, memory size is very small and it is important to reduce memory amount for execution of application programs. For multi-threaded applications, stack may consume a large amount of memory because each thread has its own stack of sufficiently large size for worst case. This paper presents an implementation of single stack multi-threading, called SSThread (Single Stack Thread), by sharing a stack for all threads to reduce stack memory size. By using SSThread, multi-threaded applications can be programmed based on normal C language environment and there is no requirement of transporting multi-threading operating systems. It consists of several library functions and various C macro definitions. Even though some functional restrictions in comparison to operating systems supporting complete multi-thread functionalities, it is very useful for small embedded systems with tiny memory size and it is simple to setup programming environment for multi-thread applications.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.6
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• pp.519-524
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• 2007

The OBC(on-board computer) of a satellite which plays a role of the controller for the satellite should be equipped with preventive measures against transient errors caused by SEU(single event upset). Since memory devices are pretty much susceptible to these transient errors, it is essential to protect memory devices against SFU. A common method exploits an error detection and correction code and additional memory devices, combined with periodic memory scrubbing. This paper proposes an effective memory scrubbing scheme for the OBC of STSAT-2. The memory system of the OBC is briefly mentioned and the reliability of the information stored in the memory system is analyzed. The result of the reliability analysis shows that there exist optimal scrubbing periods achieving the maximum reliability for allowed overall scrubbing overhead and they are dependent on the significance of the information stored. These optimal scrubbing periods from a reliability point of view are derived analytically.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.6
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• pp.425-432
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• 2004

In this paper, we introduce the analog memory fabricated in a 0.35${\mu}{\textrm}{m}$ single poly standard CMOS process. We measured the programming characteristics of the analog memory cell such as linearity, reliability etc. Finally, we found that the characteristics of the programming of the cell depend on the magnitude and the width of the programming pulse, and that the accuracy of the programming within 10mV is feasible under the optimal condition. In order to standardize the characteristics of the cell, we have investigated numbers of cells. Thus we have used a program named Labview and a data acquisition board to accumulate the data related to the programming characteristics automatically.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.10
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• pp.10-16
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• 2008

Generally, the satellite circling round in a low orbit goes through Van Allen belt connecting with the magnetic fold, in which electronic components are easily damaged and shortened by charged particles moving in a cycle between the South Pole and the North Pole. In particular, Single Event Upset(SEU) by radiation could cause electronic device on satellite to malfunction. Based on the idea mentioned above, this study considersabout SEU effect on the On-board Computer(OBC) of STSAT-1 in the space environment radiation, and shows algorithm to cope with SEUs. In this experiment, it also is shown that the repetitive memory read/write operation called memory wash is needed to prevent the accumulation of SEUs and the choice for the period of memory wash is examined. In conclusion, it is expected that this research not only contributes to understand low capacity of On-board Computer(OBC) on Low Earth Orbit satellite(LEOS) and SaTReC Technology satellite(STSAT) series, but also makes good use of each module development of Korea Multi-Purpose Satellite(COMPSAT) series.