• Title/Summary/Keyword: Single event upset

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A Study on the SEU in the SRAM to proton Irradiation

  • Lho, Young-Hwan;Park, Bo-Kyun;Kim, Bong-Sun
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.2295-2297
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    • 2003
  • The major problem encountered in satellite design is EMI (Electro-Magnetic Interference) and EMC (Electro-Magnetic Compatibility). Here, our focus is on the effects of protons on the electronic system. The SEU (Single Event Upset) results from the level change of stored information due to photon radiation and temperature in the space and the nuclear power plant environment. The impact of SEU on PLD (Programmable Logic Devices) technology is most apparent in ROM/SRAM/DRAM devices wherein the state of storage cell can be upset. In this paper, a simple and powerful test techniques is suggested, and the results are presented for the analysis and future reference. The test results are compared with that of JPL test report. In our experiment, the proton radiation facility available at KIRAMS (Korea Institute of Radiological Medical Sciences) has been applied on a commercially available SRAM manufactured by Hynix Semiconductor Company.

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The Implementation of Testing Board forSingle Event Upsets

  • Lho, Young-Hwan;Kim, Ki-Yup
    • International Journal of Aeronautical and Space Sciences
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    • v.5 no.2
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    • pp.28-34
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    • 2004
  • One of the major problem encountered in nuclear plants and satellites design isEMI (Electro-Magnetic Interference) and EMC (Electro-Magnetic Compatibility).Here, our focus is to implement the test board for checking SEU (Single EventUpsets); the effects of protons on the electronic system. The SEU results from thelevel change of stored information due to photon radiation and temperature in thespace environment. The impact of SEU on PLD (Programmable Logic Devices)technology is most apparent in ROM/SRAM/DRAM devices wherein the state ofstorage cell can be upset. In this paper, a simple and powerful test techniques issuggested, and the results are presented for the analysis and future reference. In ourexperiment, the proton radiation facilitv (having the energy of 50 MeV with a beamcurrent of 60 uA of cyclotron) available at KIRAMS (Korea Institute of RadiologicalMedical Sciences) has been applied on a commercially available SRAM manufacturedby Hynix Semiconductor Company.

비동기 디지털 시스템의 고장 진단 및 극복 기술 동향

  • Gwak, Seong-U;Yang, Jeong-Min
    • ICROS
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    • v.17 no.4
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    • pp.35-41
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    • 2011
  • 비동기적으로 동작하는 디지털 회로는 동기 순차 회로에 비해서 고속, 저전력 소비 등 여러 가지 장점을 지니기 때문에 현대 디지털 시스템에서 여전히 중요한 요소로 사용되고 있다. 본 기고에서는 비동기 순차 회로에서 발생하는 고장을 진단하고 극복하는 최신 기술을 소개한다. 본 기고에서 주로 다루는 기술은 '교정 제어'로서 피드백 제어의 원리를 이용하여 비동기 순차 회로의 안정 상태를 바꾸는 기법이다. 크리티컬 레이스(critical race), 무한 순환 등 비동기 회로 설계상의 오류를 포함하여 SEU(Single Event Upset), 총이론화선량(TID)에 의한 고장 등 외부 환경에 의해서 발생하는 비동기 회로의 고장을 교정 제어를 이용하여 진단하고 극복하는 기술에 대해서 알아본다.

Soft error correction controller for FPGA configuration memory (FPGA 재구성 메모리의 소프트에러 정정을 위한 제어기의 설계)

  • Baek, Jongchul;Kim, Hyungshin
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.11
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    • pp.5465-5470
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    • 2012
  • FPGA(Field Programmable Gate Array) devices are widely used due to their merits in circuit development time, and development cost. Among various FPGA technologies, SRAM-based FPGAs have large cell capacity so that they are attractive for complex circuit design and their reconfigurability. However, they are weak in space environment where radiation energy particles cause Single Event Upset(SEU). In this paper, we designed a controller supervising SRAM-based FPGA to protect configuration memory inside. The controller is implemented on an Anti-Fusing FPGA. Radiation test was performed on the implemented computer board and the result show that our controller provides better SEU-resilience than TMR-only system.

Engineering Model Design and Implementation of Mass Memory Unit for STSAT-2 (과학기술위성 2호 대용량 메모리 유닛 시험모델 설계 및 구현)

  • Seo, In-Ho;Ryu, Chang-Wan;Nam, Myeong-Ryong;Bang, Hyo-Choong
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.33 no.11
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    • pp.115-120
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    • 2005
  • This paper describes the design and implementation of engineering model(EM) of Mass Memory Unit(MMU) for Science and Technology Satellite 2(STSAT-2) and the results of integration test. The use of Field-Programmable Gate Array(FPGA) instead of using private electric parts makes a miniaturization and lightweight of MMU possible. 2Gbits Synchronous Dynamic Random Access Memory(SDRAM) module for mass memory is used to store payload and satellite status data. Moreover, file system is applied to manage them easily in the ground station. RS(207,187) code improves the tolerance with respect to Single Event Upset(SEU) induced in SDRAM. The simulator is manufactured to verify receiving performance of payload data.

SEU Mitigation Strategy and Analysis on the Mass Memory of the STSAT-3 (과학기술위성 3호 대용량 메모리에서의 SEU 극복 및 확률 해석)

  • Kwak, Seong-Woo
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.45 no.4
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    • pp.35-41
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    • 2008
  • When memory devices are exposed to a space environment. they suffer various effects such as SEU(Single Event Upset). For these reasons, memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, the error detection and correction strategy in the Mass Memory Unit(MMU) of the STSAT-3 is discussed. The probability equation of un-recoverable SEUs in the mass memory system is derived when the whole memory is encoded and decoded by the RS(10,8) Reed-Solomon code. Also the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. The analyzed results can be used to determine the period of scrubbing the whole memory, which is one of the important parameters in the design of the MMU.

Development of Error-Corrector Control Algorithm for Automatic Error Detection and Correction on Space Memory Modules (우주용 메모리의 자동 오류극복을 위한 오류 정정기 제어 알고리즘 개발)

  • Kwak, Seong-Woo;Yang, Jung-Min
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.5
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    • pp.1036-1042
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    • 2011
  • This paper presents an algorithm that conducts automatic memory scrubbing operated by dedicated hardwares. The proposed algorithm is designed so that it can scrub entire memory in a given scrub period, while minimally affecting the execution of flight softwares. The scrub controller is constructed in a form of state machines, which have two execution modes - normal mode and burst mode. The deadline event generator and period tick generator are designed in a separate way to support the behavior of the scrub controller. The proposed controller is implemented in VHDL code to validate its applicability. A simple version of the controller is also applied to mass memory modules used in STSAT-3.

HAUSAT-2 SPACE RADIATION ENVIRONMENT AND EFFECTS ANALYSIS (HAUSAT-2 우주방사능 환경과 영향 분석)

  • Jung Ji-wan;Chang Young-Keun
    • Bulletin of the Korean Space Science Society
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    • 2005.04a
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    • pp.143-147
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    • 2005
  • This paper describes the analysis of radiation environment and effects. TID(Total ionizing Dose) and SEE(Single Event Effects) analysis are implemented. The HAUSAT-2 is a 25kg class nanosatellite which is operated at sun-synchronous orbit at an altitude 650km. Trapped proton and Electron, Solar Proton, Galactic Cosmic Ray models are considered to HAUSAT-2 radiation environment model. Total Dose-depth curve provides TID degree and components are verified by DMBP method and Sectoring analysis. SEE are analysed with Radiation Test Report. Existing Radiation Test Reports are use to SEE analysis of HAUSAT-2.

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Engineering Model Design and Implementation of STSAT-2 On-board computer (과학기술위성 2호 탑재 컴퓨터의 EM 개발 및 구현)

  • Yu, Chang-Wan;Im, Jong-Tae;Nam, Myeong-Ryong
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.34 no.2
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    • pp.101-105
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    • 2006
  • The Engineering Model of STSAT-2 on-board computer(OBC) was developed and tested completely with other sub-systems. The on-board computer of STSAT-2 has a high- performance PowerPC processors and a structure of centralized network communication. In addition, a lot of logics are implemented by Field Programmable Gate Array, such as interrupt controller, watchdog timer and UART. It could make the weight and size of OBC lighter and smaller. Also, the STSAT-2 on-board computer has more improved tolerance against Single Event Upsets and faults than that of the STSAT-1.

Design of Radiation Hardened Shift Register and SEU Measurement and Evaluation using The Proton (내방사선용 Shift Register의 제작 및 양성자를 이용한 SEU 측정 평가)

  • Kang, Geun Hun;Roh, Young Tak;Lee, Hee Chul
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.8
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    • pp.121-127
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    • 2013
  • Memory devices including SRAM and DRAM are very susceptible to high energy radiation particles in the space. Abnormal operation of the devices is caused by SEE or TID. This paper presents a method to estimate proton SEU cross section representing the susceptibility of the latch circuit that the unit cell of the SRAM and proposes a new latch circuit to mitigate the SEU. 50b shift register was fabricated by using the conventional latch and the proposed latch in $0.35{\mu}m$ process. Irradiation experiment was conducted at KIRAMS by using 43MeV proton beam. It was found that the proposed latch-shift register is not affected by the radiation environment compared to the conventional latch-shift register.