• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.302-312
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• 2001

As the data transfer rate between chips gets higher, both crosstalk and SSN (Simultaneous Switching Noise) deteriorate seriously the performance of a system. The proposed interface scheme uses P-CTR and N-CTR(Positive/Negative Constant Transition Rate) which encodes data at both falling and rising edges, where the transition directions of N-CTR and P-CTR are opposite. And the proposed bus system places two P-CTR drivers and two N-CTR drivers alternatively. In the proposed P/N-CTR interface scheme, the signals of neighboring interconnection lines at both sides of a bus will not switch simultaneously in the same direction, which leads to reduction in the maximum crosstalk and SSN compared to conventional interfaces. For verification of noise reduction of the proposed interface scheme, the scheme is applied to several kinds of bit-wide buses with various interconnection structures, and HSPICE simulation was performed with 0.35 ${\mu}{\textrm}{m}$ SPICE parameters. The simulation results show that in the 32-bit or less wide bus, the maximum SSN and crosstalk are reduced to at least 26.78% and 50%, respectively in comparison with the conventional interface scheme.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.11-12
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• 2008

최근 LSI speed의 고속화에 따라, SSN (Simultaneous Switching Noise)이 매우 큰 문제가 되고 있다. 이에 PDN에 대한 많은 해결책들이 제시되고 있으나 가장 저비용 고효율을 지향할 수 있는 방법이 현재 사용되고 있는 유기기판에 Capacitor를 내장하여 로 사용하는 방법이다. Decoupling capacitor를 두께가 밟은 유기기판에 구현하기 위해서는 유전율이 큰 물질을 사용하는 것이 좋은데 본 연구에서는 $BaTiO_3$를 epoxy 에 혼합하여 10um 두께의 필름으로 제작한 후 유기기판 제조 공정에 사용하여 유기기판을 구현하였다. 이렇게 구현된 capacitor 내장 유기기판을 2 stub의 간단한 회로를 구현하여 유전율 등을 측정하였으며, 고주파 전산모사를 통하여 capacitor의 용량 변화에 따른 고주파 특성의 변화를 연구하였다.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.42-46
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• 2014

In this paper, a coil typed electromagnetic band gap (EBG) structure to be inserted in the printed circuit board (PCB) inner layer in order to stabilize the PCB power line is proposed and implemented for global-navigation satellite service (GNSS) with the bandwidth from 1.55GHz to 1.81GHz. From the measurement result of the PCB board including EBG structure, the insertion loss(S21) was measured below about -50dB. From these results, it is expected that the stabilization of power delivery network (PDN) structure in the PCB circuit design should be improved and the preparation to EMI will be effective.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.152-160
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• 2013

In this paper, to the aim of wideband SSN(Simultaneous Switching Noise) suppression characteristic, investigation of spiral resonator are used in conjunction with bead which is commonly used for noise suppression method. Bead works effectively to suppress the power noise up to the first harmonic of fundamental frequency, 0.8 GHz, and spiral resonator suppress noise well in the frequency range of SRF(Self Resonance Frequency) which is inversely proportional to the length of spiral. Thus, when bead used in conjunction with a spiral the noise suppression characteristic is determined by the one of higher impedance element of the two in the frequency range and achieves more broadband filtering characteristic. The case for using 22 nH bead turns out 4.8, 2.0, 0, and, 0.6 dB, and the case for using 22 nH bead in conjunction with 3-turns spiral achieves more wideband characteristic of 9.5, 8.3, 6.1, and 9.9 dB power noise suppression performances at the first, second, third, and fourth harmonics, respectively. The peak-to-peak voltage levels decrease from 76 mV to 56 mV using 22 nH bead, and the level decrease rapidly to 34 mV when using in conjunction with bead and 3-turn spiral. Thus more wideband SSN suppression characteristic can be achieved using bead with spiral.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.1
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• pp.27-32
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• 2015

In this paper, a mushroom typed electromagnetic band gap (EBG) structure to be inserted in the printed circuit board (PCB) inner layer in order to stabilize the PCB power line is proposed for global-navigation satellite service (GNSS). In designing the proposed EBG structure, the target stop-bandwidth was designed from 1.55GHz to 1.81GHz including GNSS and mobile communication-related frequency bandwidth. In this bandwidth, the insertion loss(S21) was observed below about -40dB. From the simulation results, it is expected that the stabilization of power delivery network (PDN) structure in the PCB circuit design should be improved and the effective correspondence to EMI will be helpful.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.5
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• pp.927-934
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• 2019

Recently, mobile devices have evolved into small computers with various functions according to user requirements. Careful attention must be paid to the design of the power supply network for the stable operation of the application processor (AP), the wireless communication modem, the high performance camera, and the various interfaces of the mobile device to implement various functions of the mobile device. In this paper, we analyzed and verified the method of optimizing the design parameters such as the position, capacity, and number of decoupling capacitors to meet the target impedance required by the driver IC chip to ensure the stability of the power supply network of mobile devices that should be designed as wiring type due to mounting density limitation. The proposed wired power supply network design method can be applied to various applications including high-speed signal transmission line in addition to mobile applications.