• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.23-32
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• 2006

Fast and accurate power bus design (FAPUD) method for multi-layers high-speed digital boards is devised for the power supply network design tool for accurate and precise high speed board. FAPUD is constructed, based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching can be carried out because the I/O switching effect on a power supply noise can be estimated over the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.113-117
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• 2003

The digital systems include the noise in power supply, ground and packaging due to a simultaneous switching of signal, signal reflections and distortions on single and multiple transmission lines. The requirement for the controlled impedance on a PCB can be both a critical success factor and a design challenge. So, the invented tool simulates the tracks controlled impedance with the test coupon. It can saves the design time and supports the economical PCB design.

• The Transactions of the Korea Information Processing Society
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• v.7 no.7
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• pp.2179-2187
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• 2000

This paper provides a heuristic analysis technique which determines an optimal number of V\ulcorner/V\ulcorner pads meeting allowable Simultaneous Switching Noise(SN) budget, early in the design phase. Until now, in determining the number of V\ulcorner/V\ulcorner pads, designers had to simulate packaging models case by case in the design phase or roughly allocate the power/ground pins in an inaccurate way according to typical design rules. However, due to the high density and frequency trends of IC technologies, the V\ulcorner/V\ulcorner pads allocation method can affect an adverse effect on IC operations, which requires more accurate and efficient methods be devised. Thus, this paper proposes an analytic V\ulcorner/V\ulcorner pads calculation method that gives a practical help for packaging designs early in the design phase. The proposed method is applied to a design example of a 1/8x208 pin plastic quad flat package (PQFP) and the results are verified through simulation using HSPICE.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.9
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• pp.4223-4239
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• 2016

In this paper, we consider an amplify-and-forward (AF) full-duplex relay network (FDRN) using simultaneous wireless information and power transfer, where a battery-free relay node harvests energy from the received radio frequency (RF) signals from a source node and uses the harvested energy to forward the source information to destination node. The time-switching relaying (TSR) protocol is studied, with the assumption that the channel state information (CSI) at the relay node is imperfect. We deliver a rigorous analysis of the outage probability of the proposed system. Based on the outage probability expressions, the optimal time switching factor are obtained via the numerical search method. The simulation and numerical results provide practical insights into the effect of various system parameters, such as the time switching factor, the noise power, the energy harvesting efficiency, and the channel estimation error on the performance of this network. It is also observed that for the imperfect CSI case, the proposed scheme still can provide acceptable outage performance given that the channel estimation error is bounded in a permissible interval.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.7
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• pp.786-795
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• 2010

In this paper, we propose a new EBG structure that the two unit cells are connected by the bridge line in signal transmission plane. The SSN of the power plane is reduced effectively by via holes and bridge lines connecting the unit cells. The superior signal transfer characteristic is shown between the signal lines in the signal transmission plane. The proposed EBG structure contains 1.2 GHz cut-off frequency and less than －30 dB suppression in the 8.3 GHz broad bandwidth. In addition, To improve the SI(Signal Integrity) in signal transmission plane keeping the same bandstop frequency range, the optimized location of the reference plane is proposed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.279-282
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• 2000

As digital systems continue to use components with faster edge rates and clock speeds, transmission of the digital information in these systems approaches the microwave realm. At these speeds digital signal fidelity becomes both a critical success factor and design challenge. The noise sources in digital systems include the noise in power supply, ground and packaging media due to simultaneous switching of drivers, signal reflections and distortions on single and multiple transmission lines. This paper presents theory, case studies and design considerations of gigabit interconnection for network and communication systems. The case studies show HSPICE and Ampredictor simulations of alternate approaches. Various subjects including skin effect and dielectric losses, interconnect simulations and crosstalks of connector, affected signal discontinuity, are addressed.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1601_1602
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• 2009

본 논문은 SSN(Simultaneous Switching Noise) 이 유전체를 통해 다른 시스템에 유기되는 것을 막기 위한 방법인 EBG(Electromagnetic Band-Gap)에 관한 연구이다. 이에 대한 EBG 구조를 설계하기 위해 PDN(Power Delivery Network)에 주기적인 패턴을 삽입한다. 패키지에 EBG 구조를 적용하기 위해 인쇄 회로기판 범위에서 연구되었던 구조를 변형 및 개조하여 EBG 구조가 내포하고 있는 필터의 차단 주파수의 범위를 넓히며 차단 시작 주파수를 1GHz 아래로 낮추는 소형화 방법을 모색한다. 이 연구에서 실시할 EBG 구조에 대한 간단한 고찰과 인쇄 회로 기판에 적합한 AI-EBG(Alternating impedance Electromagnetic Band-Gap) 구조를 이용한 EBG 의 소형화에 대해 언급하고, 소형화를 위한 3-D EBG 의 설계구조에 대해 설명한다. 그리고 저주파에서 차단특성을 높이기 위한 방법으로 3-D EBG를 사용하고 AI-EBG와 비교하여 차단특성의 변화를 Full-wave 시뮬레이션과 측정으로서 비교한다.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.51-54
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• 2002

As digital systems continue to use components with faster edge rate and clock speeds, transmission of the digital information can take place many troubles. The increasing requirement for controlled impedance PCBs becomes both a critical success factor and a design challenge. Especially, the noise sources in digital system include the noise in power supply, ground and packaging due to simultaneous switching of signal, signal reflections and distortions on single and multiple transmission lines. This paper simulates the tracks controlled impedance with the test coupon. So, it can saves the design time and supports the economical PCB design.