• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.15-24
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• 2012

In this paper, we suggest the dynamic-response-free SMPS using a new high-resolution DPWM generator based on switched-capacitor delay technique. In the proposed system, duty ratio of DPWM is controlled by voltage slope of an internal capacitor using switched-capacitor delay technique. In the proposed circuit, it is possible to track output voltage by controlling current of the internal capacitor of the DPWM generator through comparison between the feedback voltage and the reference voltage. Therefore the proposed circuit is not restricted by the dynamic-response characteristic which is a problem in the existing SMPS using the closed-loop control method. In addition, it has great advantage that ringing phenomenon due to overshoot/undershoot does not appear on output voltage. The proposed circuit can operate at switching frequencies of 1MHz~10MHz using internal operating frequency of 100 MHz. The maximum current of the core circuit is 2.7 mA and the total current of the entire circuit including output buffer is 15 mA at the switching frequency of 10 MHz. The proposed circuit has DPWM duty ratio resolution of 0.125 %. It can accommodate load current up to 1 A. The maximum ripple of output voltage is 8 mV. To verify operation of the proposed circuit, we carried out simulation with Dongbu Hitek BCD $0.35{\mu}m$ technology parameter.

• Journal of the Korea Society of Computer and Information
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• v.16 no.2
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• pp.141-151
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• 2011

This paper suggests the Facility Management System for plant factory promising to be a core technology of the agriculture in the future. This system makes diagnoses that status from sensors or facilities in the factory for exact operation and monitors the internal environment with the control status in real-time. It is expected that we could operate a plant factory safely and effectively by using the system. The system consists of the data management module, the context provider module, the context interpreter module, the service provider module, the data storage and user interface. The system provide with the failure diagnosis service, the facility control service, and the high-reliability monitoring service via the interactions between above modules. The failure diagnosis service determines whether the sensors or facility devices are in failure or not, and informs the administrator of their conditions. The facility control service is activated in case if the facilities need to be managed during the diagnosis for failure or malfunction processes. The high-reliability monitoring service provides the administrator with verified data through the failure diagnosis service. Then we confirmed that the suggested system operates correctly through the system simulation.

• Journal of the Korea Society of Computer and Information
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• v.17 no.5
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• pp.1-7
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• 2012

In this paper, we design and implement the simulator for WAN storage replication model performance evaluation in cloud computing environment. Each cloud of simulator is composed of virtual machine emulator and storage emulator. The virtual machine emulator is composed of read/write ratio module, the read/write sequence combination module, and the read/write request module. The storage emulator is composed of storage management module, data transfer module, read/write operations module, and overhead processing module. Using the simulator, we evaluate performance of migration scheme, pre-copy and the post-copy, considering about read/write ratio, network delay, and network bandwidth. Through simulation, we have confirmed that the average migration time of pre-copy was decreased proportional to the read operation. However, average migration time of post-copy was on the increase. Also, the average migration time of post-copy was increased proportional to the network delay. However, average migration time of pre-copy was shown uniformly. Therefore, we show that pre-copy model more effective to reduce the average migration time than the post-copy model. The average migration time of pre-copy and post-copy were not affected by the change of network bandwidth. Therefore, these results show that selects the storage replication model to be, the network bandwidth know not being the important element.

• Journal of Korean Society of Transportation
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• v.30 no.5
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• pp.23-31
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• 2012

The objective of this study is to develop the design criteria of traffic island considering pedestrian level of service (LOS). In pursuing the above, this study gives particular emphasis to suggesting the minimum design space of traffic island in order to maintain pedestrian LOS C and D, and the critical pedestrian traffic volume that reflects the intersection geometry (2 lanes per direction) through the simulation analysis. The main results are as follows. First, the spaces of 160 traffic islands, which meet the pedestrian LOS C and D and reflects the pedestrian traffic volume by signal cycle, are drawn by using a commercial simulator VISSIM. The relevant spaces of traffic island in terms of both the pedestrian LOS and the pedestrian traffic volume are evaluated to range from $3.0m^2$ to $41m^2$. Second, the critical pedestrian traffic volume for the operation of traffic island is evaluated to be 1,000-1,300 person/hour at LOS C and 1,600-1,800 person/hour at LOS D, respectively, when a cycle of 120-150 seconds were applied to a intersection with two lanes per direction.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.78-86
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• 1999

In this paper, a distributed arithmetic digital neural network with learning and testing phase implemented in a body has been studied. The proposed technique is based on the two facts; one is that the weighting coefficients adjusted will be stored in registers without shift, because input values or input patterns are not changed while learning and the other is that the input patterns stored in registers are not changed while testing. The proposed digital neural network is simulated by hardware description language such as VHDL and verified the performance that the neural network was applied to the recognition of seven-segment. To verify proposed neural networks, we compared the learning process of modified perceptron learning algorithm simulated by software with VHDL for 7-segment number recognizer. The results are as follows: There was a little difference in learning time and iteration numbers according to the input pattern, but generally the iteration numbers are 1000 to 10000 and the learning time is 4 to 200$\mu\textrm{s}$. So we knew that the operation of the neural network is learned in the same way with the learning of software simulation, and the proposed neural networks are properly operated. And also the implemented neural network can be built with less amounts of components compared with board system neural network.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.99-108
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• 2015

The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.55-63
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• 2015

Recently, terroristic threats using a radio controlled improvised explosive device (RCIED) that is remotely controlled and exploded have been increased around the world. In order to prevent the explosion of an RCIED, jamming techniques that interrupt an RCIED receiver can be used, so that the receiver can not demodulate the trigger code. Conventional jamming technique is a type of active barrage jamming that always emits the noise jamming signal for all the frequency band. However, it needs large power consumption and thus is limited in operation time for a vehicle. In order to overcome the shortage of the active barrage jamming, reactive jamming technique has drawn attention. In reactive jamming, all the frequency band is firstly scanned, and then if any trigger signal exists, one emits the jamming signal to the corresponding frequency band. Therefore, the reactive jamming is superior to the active barrage jamming in terms of power efficiency. However, a reactive jammer emits a jamming signal only after the trigger signal is intercepted, which means that the jamming signal may be late for interrupting an RCIED receiver. In this sense, it is needed to evaluate a delay in an RCIED receiver. To achieve this, we analyze the reaction time and present the simulation result for jamming performance of reactive jamming against an RCIED using mobile devices.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.34-42
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• 2012

This paper analyses the energy saving basic power models in core IP networks, and proposes the adaptive buffer and burst scheme which is a possible energy saving method, and its implementation algorithm in core IP networks. Especially this paper describes the adaptive buffer and burst scheme dynamically varying the buffering interval B according to the input traffic volume of ingress router, and explains the operation principle of proposed scheme. This method is to adjust the buffering interval B according to input traffic volume of ingress router, that is increasing the interval B when input traffic volume is low, and decreasing the interval B when input traffic volume is high between some given interval regions. This method can gets the high energy saving effect as decreasing the transition number of idle/active in networks when input traffic volume is low, and decreasing the transition number of idle/active by the continuous of burst packets in transit router when input traffic volume is high. This paper shows the increasing of asleep rate for the energy saving of core IP networks and confirms the energy saving of core IP networks by the computer simulation. We confirmed that proposed method can be save the energy of IP networks by properly trade off network performances.