• 대한설비공학회지:설비저널
• /
• 제17권3호
• /
• pp.238-248
• /
• 1988

The flow pattern inside the power condenser is generally known to be very complicated due to the phase change and turbulence effects as well as the effect of condenser geometry. In the present study, the flow pattern inside the power condenser was numerically simulated with a personal computer. The widely known CHAMPION 2/E/FIX(Concentration, Heat and Momentum Program Instruction Outfit, 2D/Elliptic/Fixed grid) computer code was modified for this purpose. The flow was asssumed to be two-dimensional and steady-state, and the tube bank was considered to be homogeneous porous medium. Simple turbulent diffusion coefficients based on the appropriate experiments were obtained for the computation. Through this analytical approach, the flow pattern could be predicted fairly well. The computational results also show that the location of the air vent plays an important key role in determining the efficiency of the condenser.

• Progress in Superconductivity
• /
• 제5권1호
• /
• pp.21-25
• /
• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• 전자공학회논문지A
• /
• 제31A권10호
• /
• pp.132-140
• /
• 1994

In this paper, we consider the area-minimal implementation of the instruction decoder for microprogrammed processors such as modern CISC-type microprocessor. We formulate it as a constrained output encoding problem and, based on simulated annealing algorithm, propose efficient heuristic solution methods both for PLA and multi-level implementation of the decoder. Experimental results on various examples show that our methods produce, on the average, 10~40% reduction of the number of product terms for the PLA implementations and 9.8~34.4% reduction of the number of literal for the multi-level implementations compared to the results of random encoding method.

• ETRI Journal
• /
• 제24권5호
• /
• pp.391-397
• /
• 2002

This paper presents digital signal processor (DSP) instructions and their data processing unit (DPU) architecture for high-speed fast Fourier transforms (FFTs) in orthogonal frequency division multiplexing (OFDM) systems. The proposed instructions jointly perform new operation flows that are more efficient than the operation flow of the multiply and accumulate (MAC) instruction on which existing DSP chips heavily depend. We further propose a DPU architecture that fully supports the instructions and show that the architecture is two times faster than existing DSP chips for FFTs. We simulated the proposed model with a Verilog HDL, performed a logic synthesis using the 0.35 ${\mu}m$ standard cell library, and then verified the functions thoroughly.

• 전자공학회논문지A
• /
• 제31A권6호
• /
• pp.199-208
• /
• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• 전자공학회논문지C
• /
• 제34C권12호
• /
• pp.9-19
• /
• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• 대한전자공학회논문지
• /
• 제23권1호
• /
• pp.101-113
• /
• 1986

In this paper, a real-time pitch detector LPC vocoder as implemented on a high speed digital signal processor, NEC 7720, is described. The pitch detector was based mainly on the SIFT algorithm. The SIFT pitch detector consists primarily of a digital low pass filter, inverse filter, computation of autocorrelation, a peak picker, interpolation, V/UV defcision and a final pitch smoother. In our approach, modification, mainly on the V/UV decision and a final pitch smoother, was made to estimate more accurate pitches. An 16-bit fixed-point aithmatic was employed for all necessary computation and the simulated results were compared with the eye detected pitches obtained from real speech data. The pitch detector occupies 98.8% of the instruction ROM, 37% of the data ROM, and 94% of internal RAM and takes 15.2ms to estimate a pitch when an analysis frame is consisted of 128 sampled speech data. It is observed that the tested results were well agreed with the computer simulation results.

• 한국재난정보학회 논문집
• /
• 제5권2호
• /
• pp.50-73
• /
• 2009

This paper is about the establishment of "Initial Response System." Initial response system is most important and should be treated urgently among all preparations for chemical terrorism. The objects of Initial response system are to protect civilians and the first responder who are exposed directly to chemical terrorism. Therefore, this paper suggests two main issues about Initial response system. One is to prepare immediate and exact information service system which assures the safety and survival of exposed people. The other is to build Scene Response System integrated with Command-Control Procedure for early finished situation. Compared to United States, overcoming the Chemical Terrorism requires to improve the contents of two categories: Counter Citizen Response part and Initial Scene Response part. For Counter citizen response part' s sake, the web-sites of Response leader agencies for searching information about chemical terrorism should be modified specifically. These web-sites have to be re-organized in detail. The existing Information service system which has been vaguely informed as "CBRNE Accident" needs to be divided as "CBRNE Accident" and "WMD terrorism." Further, each of them should be specialized in "Chemical', "Biological", and "Radiological" categories. There is a need to rearrange current Emergency Instruction for civilians against chemical terrorism in feasible way. At the same time, it should be applied consistently to all organizations through agreement between experts and related-organizations. For Initial Scene Response part's sake, "Initial scene response procedure (SOP)" and "Operational conception" should be produced through Simulated Exercises and workshops of all organizations related with initial response. These organizations have to cooperate with Ministry of Environment which is the main leader Agency as the center. Next, there is a need to develop a technology and Scene Response Equipments, and to standardize the response equipments which consider the capability of First Responders for chemical terrorism. Especially, improving capability of equipments is required to overcome the vulnerability of Scene Response Equipments.

• 한국컴퓨터정보학회논문지
• /
• 제13권4호
• /
• pp.87-95
• /
• 2008

경계면 스캔 구조는 시험대상회로의 출력 값들을 캡쳐하여 스캔경로를 이용하여 TDO로 직렬출력하여 출력 값을 관찰할 수 있는 시험구조이며, Sample/preload명령어를 이용하여 시험대상회로의 특정한 한 순간의 출력만을 캡쳐하여 직렬출력하여 분석할 수 있다. 본 논문에서는 4비트 비동기 카운터회로를 시험대상회로로 선정하고, 정상동작중인 카운터의 특정 출력을 지정하여 특정한 순간의 정적인 출력이 아닌, 연속적인 동적인 출력 값들을 다른 출력결과의 영향 없이 지속적으로 TDO로 출력하여 관찰할 수 있는 선택 가능한 관측점을 가진 시험구조와 시험절차를 개발하였다. 본 논문에서 제안하는 선택 가능한 관측점을 가진 시험구조는 표준에서 정한 시험동작을 정상적으로 수행하며, 관측점의 설정을 위한 명령어가 추가되었다. 4비트 카운터회로에 제안된 선택 가능한 관측점 시험구조를 적용 설계하고, 관측점 설정 명령어를 사용한 시험절차를 Altera의 Max 10.0을 이용한 시뮬레이션을 통해 동작의 정확성을 확인하였다.

• 한국보육지원학회지
• /
• 제11권2호
• /
• pp.177-200
• /
• 2015

본 연구는 '4세 누리과정 교사용 지도서' 신체활동을 예비유아교사들의 모의수업을 통해 분석하고자 하였으며, 그에 따른 결과로 유아교육현장에 누리과정 교사용 지도서의 신체활동을 수업으로 실시하는데 있어 도움을 주고자 실시된 연구이다. 연구 참여자는 경기도 K대학의 유아교육과 2학년 2학기에 재학 중인 30명을 대상으로 선정하였다. '4세 누리과정 교사용 지도서'의 신체활동 분석을 위해 비형식적 면담과 예비유아교사의 반성적 저널 그리고 30회기의 수업평가서 등의 자료 수집을 통해 질적 연구를 실시하였다. 연구결과, '4세 누리과정 교사용 지도서'의 신체활동 분석으로 예비유아교사들은 첫째, '4세 누리과정 교사용 지도서' 신체활동의 주된 목표를 '표현하기'로 인식하고 있음을 볼 수 있었으며, 둘째, '4세 누리과정 교사용 지도서' 신체활동에 제시된 보조 자료인 '동영상, 그림책, 음원, 그림 자료' 등을 수업에 활용하는데 있어 신중한 판단이 요구되는 것으로 보았다. 셋째, '4세 누리과정 교사용 지도서' 신체활동 실행 시 나타나는 오류나 문제점으로, '예비유아교사가 이해하기 어려운 활동'과 '제목에 따른 활동 방법이 부적합하게 제시된 활동'으로 판단하였다. 넷째, 예비유아교사들이 이해하는 '4세 누리과정 교사용 지도서'의 신체활동 개선점으로, 본 활동을 실시하기 전 기초적인 신체활동이 먼저 이루어져야 함과 수업시간에 적절한 실제물의 제시, 교사의 시범의 필요성, 그리고 신체활동을 위해서 그 상황에 필요한 규칙을 유아와 교사가 함께 만드는 것, 등이 요구된다고 하였다. 이러한 연구결과를 통해 유아교육현장의 교사들이 누리과정의 신체활동을 수업으로 실시하기 전 교사로서 깊이 있는 사고와 판단이 요구됨을 알 수 있었다.