• Electrical & Electronic Materials
• /
• v.12 no.9
• /
• pp.1-9
• /
• 1999

• Journal of Integrative Natural Science
• /
• v.3 no.1
• /
• pp.7-18
• /
• 2010

Ethylene-bridged silsesquioxane resins were synthesized from two monomers: 1,2-bis(trimethoxysilyl)ethane and methyltrimethoxysilane. The silsesquioxane thin films were spin-coated from the copolymerized resins on silicon wafer. Metal insulator metal (MIM), metal insulator semiconductor (MIS) devices were utilized to investigate the electrical properties of the copolymerized thin films. As the films were inserted as gate insulator in the OTFT devices, the field effect mobilitites were evaluated by employing Poly(3-hexylthiophene) (P3HT) as organic semiconductor, which shows that their dielectric properties and mobility values are dependent on the molecular structures and Si-OH concentration involving in the films.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.21 no.5
• /
• pp.90-99
• /
• 1984

A onetimensional distribution of the temperature and the heat source in the SOI (silicon-on-insulator) multi-layer structure illuminated by tungsten lamps from both sides was obtained by solving the heat equation in steady state on a finite difference grid using successive over-relaxation method. The heat source distribution was obtained by considering such features as spectral components of the light source, multiple reflection at the internal interfaces, temperature and frequency dependence of the light absorption coefficient, etc. The front and back surface temperatures, which are boundary conditions for the heat equation, were derived from a requirement that they satisfy the radiation conditions. The radiation flux as well as the conduction flux was considered in modelling the thermal behaviour at the internal interfaces. Since the temperature and the heat source profiles are strongly dependent upon each other, the calculation of each profile was iterated using the updated profile of the other until they are consistent with each other. The experimental temperature at the front surface of the wafer as measured by Pyrometer was about 1200$^{\circ}$K, while the simulated temperature was 1120$^{\circ}$K.

• Transactions on Electrical and Electronic Materials
• /
• v.9 no.6
• /
• pp.231-236
• /
• 2008

B, P, and Cs ions were implanted with various parameters into silicon nitride layers prepared by LPCVD. In order to get the maximum impurity concentration at the silicon nitride surface, a high temperature oxide (HTO) buffer layers was deposited prior to the implantation. Alkali ion and pH sensing properties of the layers were investigated with an electrolyte-insulator-silicon (EIS) structure using high frequency capacitance-voltage (HF-CV) measurements. The ion sensing properties of implanted silicon nitrides were compared to those of as-deposited silicon nitride. Band Cs co-implanted silicon nitrides showed a pronounced difference in pH and alkali ion sensing properties compared to those of as-deposited silicon nitride. B or P implanted silicon nitrides in contrast showed similar ion sensitivities like those of as-deposited silicon nitride.

• Journal of Sensor Science and Technology
• /
• v.3 no.2
• /
• pp.74-80
• /
• 1994

Silicon direct bonding technology is very attractive for both silicon-on-insulator devices and sensor fabrication because of its thermal stress free structure and stability. The process of SDB includes hydration of silicon wafer and heat treatment in a wet oxidation furnace. After hydration process, hydroxyl groups of silicon wafer were analyzed by using Fourier transformation-infrared spectroscopy. In case of hydrophilic treatment using a ($H_{2}O_{2}\;:\;H_{2}SO_{4}$) solution, hydroxyl groups are observed in a broad band around the 3474 $cm^{-1}$ region. However, hydroxyl groups do not appear in case of diluted HF solution. The bonded wafer was etched by using tetramethylammonium hydroxide etchant. The surface of the self etch-stopped silicon dioxide is completely flat, so that it can be used as sensor applications such as pressure, flow and acceleration, etc..

• ETRI Journal
• /
• v.17 no.4
• /
• pp.1-12
• /
• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.146-146
• /
• 2010

일반적인 MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor)은 소스와 드레인의 형성을 위해서 불순물을 주입하고 고온의 열처리 과정을 거치게 된다. 이러한 고온의 열처리 과정 때문에 녹는점이 낮은 메탈게이트와 게이트 절연막으로의 high-k 물질의 사용에 제한을 받게된다. 이와 같은 문제점을 보완하기 위해서 소스와 드레인 영역에 불순물 주입공정 대신에 금속접합을 이용한 Schottky Barrier Tunnel Transistor (SBTT)가 제안되었다. SBTT는 $500^{\circ}C$ 이하의 저온에서 불순물 도핑없이 소스와 드레인의 형성이 가능하며 실리콘에 비해서 수십~수백배 낮은 면저항을 가지며, 단채널 효과를 효율적으로 제어할 수 있는 장점이 있다. 또한 고온공정에 치명적인 단점을 가지고 있는 high-k 물질의 적용 또한 가능케한다. 본 연구에서는 p-type SOI (Silicon-On-Insulator) 기판을 이용하여 Pt-silicide 소스와 드레인을 형성하고 전기적인 특성을 분석하였다. 또한 본 연구에서는 기존의 sidewall을 사용하지 않는 새로운 구조를 적용하여 메탈게이트의 사용을 최적화하였고 게이트 절연막으로써 실리콘 옥사이드를 스퍼터링을 이용하여 증착하였기 때문에 저온공정을 성공적으로 수행할 수 있었다. 이러한 게이트 절연막은 열적으로 형성시키지 않고도 70 mv/dec 대의 우수한 subthreshold swing 특성을 보이는 것을 확인하였고, $10^8$정도의 높은 on/off current ratio를 갖는 것을 확인하였다.

• Journal of IKEEE
• /
• v.18 no.2
• /
• pp.214-219
• /
• 2014

In this paper, the usage of tilt-implanted trench Schottky diode(TITSD) based on silicon carbide is proposed. A tilt-implanted trench termination technique modified for SiC is proposed as a method to keep all the potentials confined in the trench insulator when reverse blocking mode is operated. With the side wall doping concentration of $1{\times}10^{19}cm^{-3}$ nitrogen, the termination area of the TITSD is reduced without any sacrifice in breakdown voltage while potential is confined within insulator. When the trench depth is set to 11um and the width is optimized, a breakdown voltage of 2750V is obtained and termination area is 38.7% smaller than that of other devices which use guard rings for the same breakdown voltage. A Sentaurus device simulator is used to analyze the characteristics of the TITSD. The performance of the TITSD is compared to the conventional trench Schottky diode.

• Journal of Information Display
• /
• v.6 no.2
• /
• pp.16-18
• /
• 2005

Hybrid insulator pentacene thin film transistors (TFTs) are fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layer on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility is increased to more than 35 times than that of the TFT which has only a gate insulator of $SiO_2$ at the same electric field. The carrier mobility of $1.80cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}/I_{off}$ current ratio> $1.10{\times}10^5$ are obtained less than -30 V bias condition. The result is one of the best reported performances of pentacene TFTs with hybrid insulator including cross-linked PVA layer as a gate insulator at relatively low voltage operation.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.130-130
• /
• 2011

최근 반도체 메모리 산업의 발전과 동시에 발생되는 문제들을 극복하기 위한 새로운 기술들이 요구되고 있다. DRAM (dynamic random access memory) 의 경우, 소자의 크기가 수십 나노미터 영역으로 줄어들면서, 단채널 효과에 의한 누설전류와 소비전력의 증가 등이 문제가 되고 있다. 하나의 캐패시터와 하나의 트랜지스터로 구성된 기존의 DRAM은, 소자의 집적화가 진행 되어 가면서 정보저장 능력이 감소하는 것을 개선하기 위해, 복잡한 구조의 캐패시터 영역을 요구한다. 이에 반해 하나의 트랜지스터로 구성되어 있는 1T-DRAM의 경우, 캐패시터 영역이 없는 구조적인 이점과, SOI (silicon-on-insulator) 구조의 기판을 사용함으로써 뛰어난 전기적 절연 특성과 기생 정전용량의 감소, 그리고 기존 CMOS (complementary metal oxide semiconductor) 공정과의 호환성이 장점이다. 또한 새로운 물질 혹은 구조를 적용하여, 개선된 전기적 특성을 통해 1T-DRAM의 메모리 특성을 향상 시킬 수 있다. 본 연구에서는, SOI와 SGOI (silicon-germanium-on-insulator) 및 sSOI (strained-si-on-insulator) 기판을 사용한 MOSFET을 통해, strain 효과에 의한 전기적 특성 및 메모리 특성을 평가 하였다. 그 결과 strained-Si층과 relaxed-SiGe층간의 tensile strain에 의한 캐리어 이동도의 증가를 통해, 개선된 전기적 특성 및 메모리 특성을 확인하였다. 또한 채널층의 결함이 적은 sSOI 기판을 사용한 1T-DRAM에서 가장 뛰어난 특성을 보였다.