• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.268-268
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• 2016

Chemical sensors have attracted much attention due to their various applications such as agriculture product, cosmetic and pharmaceutical components and clinical control. A conventional chemical and biological sensor is consists of fluorescent dye, optical light sources, and photodetector to quantify the extent of concentration. Such complicated system leads to rising cost and slow response time. Until now, the most contemporary thin film transistors (TFTs) are used in the field of flat panel display technology for switching device. Some papers have reported that an interesting alternative to flat panel display technology is chemical sensor technology. Recent advances in chemical detection study for using TFTs, benefits from overwhelming progress made in organic thin film transistors (OTFTs) electronic, have been studied alternative to current optical detection system. However numerous problems still remain especially the long-term stability and lack of reliability. On the other hand, the utilization of metal oxide transistor technology in chemical sensors is substantially promising owing to many advantages such as outstanding electrical performance, flexible device, and transparency. The top-gate structure transistor indicated long-term atmosphere stability and reliability because insulator layer is deposited on the top of semiconductor layer, as an effective mechanical and chemical protection. We report on the fabrication of InGaZnO TFTs with silver nanowire as the top gate electrode for the aim of chemical materials detection by monitoring change of electrical properties. We demonstrated that the improved sensitivity characteristics are related to the employment of a unique combination of nano materials. The silver nanowire top-gate InGaZnO TFTs used in this study features the following advantages: i) high sensitivity, ii) long-term stability in atmosphere and buffer solution iii) no necessary additional electrode and iv) simple fabrication process by spray.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.619-622
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• 2005

본 논문에서는 서로 다른 Si 두께 ($T_{Si}$ = 27, 50 nm) 를 갖는 SOI (Silicon On Insulator) 기판 위에 다양한 두께의 Ni/Co를 순차적으로 증착한 후 Bulk-Si과의 비교를 통해 Silicide의 형성 특성에 대하여 분석하였다. 우선 급속 열처리 (RTP, Rapid Thermal Processing) 를 통하여 Silicide를 형성한 후 측정결과 Si두께에 따라 Silicide의 특성이 달라짐을 확인하였다. 두꺼운 두께의 Si-film을 갖는 SOI 기판을 사용한 경우 증착된 금속의 두께에 따라 Bulk-Si와 비슷한 면저항 특성을 보였으나, 얇은 두께의 Si-film을 갖는 SOI기판을 사용한 경우에는 제한된 Si의 공급으로 인한 Silicide의 비저항 증가로 인하여 증착된 금속의 두께에 따라 면저항이 감소하다가 다시 증가하는 'V' 자형 곡선을 나타내었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• Journal of Sensor Science and Technology
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• v.2 no.1
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• pp.95-99
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• 1993

a-Si : H TFTs for image sensor have been fabricated and their operational characteristics have been investigated. Hydrogenated amorphous silicon nitride(a-SiN : H) films were used for the gate insulator and $n^{+}$-a-Si : H films were depostied for the source and drain contact. The thicknesses of a-SiN : H and a-Si : H films were $2000{\AA}$, respectively and the thickness of $n^{+}$-a-Si : H film was $500{\AA}$. Also the channel length and channel width of a-Si : H TFTs were $50{\mu}m$ and $1000{\mu}m$, respectively. The ON/OFF current ratio, threshold voltage, and field effect mobility of fabricated a-Si : H TFTs were $10^{5}$, 6.3 V, and $0.15cm^{2}/V{\cdot}s$, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.1-5
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• 2010

We developed a novel micro-electro mechanical systems (MEMS) test socket using silicon on insulator (SOI) substrate with the cantilever array structure. We designed the round shaped cantilevers with the maximum length of $350{\mu}m$, the maximum width of $200{\mu}m$ and the thickness of $10{\mu}m$ for $650{\mu}m$ pitch for 8 mm x 8 mm area and 121 balls square ball grid array (BGA) packages. The MEMS test socket was fabricated by MEMS technology using metal lift off process and deep reactive ion etching (DRIE) silicon etcher and so on. The MEMS test socket has a simple structure, low production cost, fine pitch, high pin count and rapid prototyping. We verified the performances of the MEMS test sockets such as deflection as a function of the applied force, path resistance between the cantilever and the metal pad and the contact resistance. Fabricated cantilever has 1.3 gf (gram force) at $90{\mu}m$ deflection. Total path resistance was less than $17{\Omega}$. The contact resistance was approximately from 0.7 to $0.75{\Omega}$ for all cantilevers. Therefore the test socket is suitable for BGA integrated circuit (IC) packages tests.

• ETRI Journal
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• v.26 no.6
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.180-184
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• 2013

In this paper, a low power antenna switch controller IC is designed using a silicon-on-insulator (SOI) CMOS technology. To improve power handling capability and harmonic distortion performance of the antenna switch, the proposed antenna switch controller provides 3-state logic level such as +VDD, GND, and -VDD for the gate and body of switch of FETs according to decoder signal. By employing input-coupled current ring oscillator and hardware efficient level shifter, the proposed controller greatly reduces power consumption and hardware complexity. It consumes 135 ${\mu}A$ at a 2.5 V supply voltage in active mode, and occupies $1.3mm{\times}0.5mm$ in area. In addition, it shows fast start-up time of 10 ${\mu}s$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.7
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• pp.394-399
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• 2016

The silicon dioxide ($SiO_2$) was deposited using various gas as oxygen and nitrous oxide ($N_2O$) in nowadays. In order to improve electrical characteristics and the interface state density ($D_{it}$) in low temperature, It was deposited with carbon dioxide ($CO_2$) and silane ($SiH_4$) gas by inductively coupled plasma chemical vapor deposition (ICP-CVD). Each $D_{it}$ of $SiO_2$ using $CO_2$ and $N_2O$ gas was $1.30{\times}10^{10}cm^{-2}{\cdot}eV^{-1}$ and $3.31{\times}10^{10}cm^{-2}{\cdot}eV^{-1}$. It showed $SiO_2$ using $CO_2$ gas was about 2.55 times better than $N_2O$ gas. After 10 years when the thin film was applied to metal/insulator/semiconductor(MIS)-nonvolatile memory(NVM), MIS NVM using $SiO_2$($CO_2$) on tunneling layer had window memory of 2.16 V with 60% retention at bias voltage from +16 V to -19 V. However, MIS NVM applied $SiO_2$($N_2O$) to tunneling layer had 2.48 V with 61% retention at bias voltage from +20 V to -24 V. The results show $SiO_2$ using $CO_2$ decrease the $D_{it}$ and it improves the operating voltage.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.393-398
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• 2014

A highly efficient dual-mode linear CMOS stacked-FET power amplifier (PA) is implemented for 3G UMTS and 4G LTE handset applications. High efficiency is achieved at a backed-off output power ($P_{out}$) below 12 dBm by employing an active-bypass amplifier, which consumes very low quiescent current and has high load-impedance. The output paths between high- and low-power modes of the PA are effectively isolated by using a bypass switch, thus no RF performance degradation occurs at high-power mode operation. The fabricated 900 MHz CMOS PA using a silicon-on-insulator (SOI) CMOS process operates with an idle current of 5.5 mA and shows power-added efficiency (PAE) of 20.5%/43.5% at $P_{out}$ = 12.4 / 28.2 dBm while maintaining an adjacent channel leakage ratio (ACLR) better than -39 dBc, using the 3GPP uplink W-CDMA signal. The PA also exhibits PAE of 35.1% and $ACLR_{E-UTRA}$ of -33 dBc at $P_{out}$ = 26.5 dBm, using the 20 MHz bandwidth 16-QAM LTE signal.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.103-103
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• 1999

CeO2 는 cubic 구조의 일종인 CeF2 구조를 가지며 격자 상수가 0.541nm로 Si의 격자 상수 0.543nm와 거의 비슷하여 Si과의 부정합도가 0.35%에 불과하여 CeO2를 Si 기판 위에 에피택셜하게 성장시킬 수 있는 가능성이 크다. 따라서 SOI(Silicon-On-Insulator) 구조의 실현을 위하여 Si 기판위에 CeO2를 에피택셜하게 성장시키려는 많은 노력이 있었다. 또한 CeO2 는 열 적으로 대단히 안정된 물질로서 금속/강유전체/반도체 전계효과 트랜지스터(MFSFET : metal-ferroelectric-semiconductor field effect transistor)에서 ferroelectric 박막과 Si 기판사이에 완충층으로 사용되어 강유전체의 구성 원자와 Si 원자들간의 상호 확산을 방지함으로써 경계면의 특성을 향상시기키 위해 사용된다. e-beam evaporation와 laser ablation에 의한 Si 기판 위의 CeO2 격자 성장에 관한 많은 보고서가 있다. 이 방법들은 대규모 생산 공정에서 사용하기 어려운 반면 RF-magnetron sputtering은 대규모 반도체 공정에 널리 쓰인다. Sputtering에 의한 Si 기판위의 CeO2 막의 성장에 관한 보고서의 수는 매우 적다. 이 논문에서는 Ce target을 사용한 reactive rf-magnetron sputtering에 의해 Si(100) 과 Si(111) 기판위에 성장된 CeO2 의 구조 및 전기적 특성을 보고하고자 한다. 주요한 증착 변수인 증착 power와 증착온도, Seed Layer Time이 성장막의 결정성에 미치는 영향을 XRD(X-Ray Diffractometry) 분석과 TED(Transmission Electron Diffration) 분석에 의해 연구하였고 CeO2 /Si 구조의 C-V(capacitance-voltage)특성을 분석함으로써 증차된 CeO2 막과 실리콘 기판과의 계면 특성을 연구하였다. CeO2 와 Si 사이의 계면을 TEM 측정에 의해 분석하였고, Ce와 O의 화학적 조성비를 RBS에 의해 측정하였다. Si(100) 기판위에 증착된 CeO2 는 $600^{\circ}C$ 낮은 증착률에서 seed layer를 하지 않은 조건에서 CeO2 (200) 방향으로 우선 성장하였으며, Si(111) 기판 위의 CeO2 박막은 40$0^{\circ}C$ 높은 증착률에서 seed layer를 2분이상 한 조건에서 CeO2 (111) 방향으로 우선 성장하였다. TEM 분석에서 CeO2 와 Si 기판사이에서 계면에서 얇은 SiO2층이 형성되었으며, TED 분석은 Si(100) 과 Si(111) 위에 증착한 CeO2 박막이 각각 우선 방향성을 가진 다결정임을 보여주었다. C-V 곡선에서 나타난 Hysteresis는 CeO2 박막과 Si 사이의 결함때문이라고 사료된다.