• 센서학회지
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• 제4권3호
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• pp.80-88
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• 1995

본 논문에서는 Al 및 TiW 금속을 상하층 전극으로 사용하고 이들 금속사이에 절연물이 존재하는 금속-절연물-금속(metal-insulator- metal : MIM) 구조의 안티휴즈 소자를 만들고 금속층간 절연물의 성질에 따른 안티휴즈 특성에 대하여 연구하였다. 금속층간 절연물로는 R.F 스퍼터링법에의해 형성된 실리콘 산화막과 탄탈륨 산화막으로 구성된 이층 절연물을 사용하였다. 이러한 안티휴즈 구조에서 실리콘 산화막은 프로그램 전의 안티휴즈 소자를 통해 흐르는 누설전류를 감소시켰으며, 실리콘 산화막에 비해 절연 강도가 낮은 탄탈륨 산화막은 안티휴즈 소자의 절연파괴전압을 저 전압으로 낮추는 역할을 하였다. 최종적으로 제조된 $Al/Ta_{2}O_{5}(10nm)/SiO_{2}(10nm)/TiW$ 구조에서 1 nA 이하의 누설전류와 약 9V의 프로그래밍 전압을 갖고 수 초내에 프로그램이 완성되는 전기적 특성이 안정된 안티휴즈 소자를 제조하였다. 그리고 이때 소자의 OFF 및 ON 저항은 각각 $3.65M{\Omega}$ 및 $7.26{\Omega}$이었다. 이와 같은 $Ta_{2}O_{5}/SiO_{2}$ 구조에서 각 절연물의 두께를 조절함으로써 측정 전압에 민감하고 재현성 있는 안티휴즈 소자를 제조할 수 있었다.

• 한국결정성장학회지
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• 제5권2호
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• pp.100-108
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• 1995

SOI구조를 얻기 위한 방법의 한가지인 ZMR공정에 있어서 열전달은 계면의 위치와 모양을 결정하는 중요한 역할을 한다. 본 연구에서는 SOI구조를 얻기 위한 ZMR공정중의 열전달 공정을 모사할 수 있는 의사정상상태 2차원 ZMR모델을 수립하였다. 본 모델은 복사, 전도 그리고 대류 열전달을 포함하며, 고/액 계면의 위치를 결정한다. 모델로부터 구한 수치해는 실리콘 기판의 용융부에서의 유동장, 전체 SOR구조에서의 온도장 그리고 실리콘 박막과 기판에서의 고/액 계면의 위치를 포함한다. 여러 공정 변수들의 변화에 따른 온도장과 계면의 형상과 폭의 변화를 알아보았다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• 전기전자학회논문지
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• 제1권1호
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• pp.1-10
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• 1997

It is well-known that rectangular bulk-Si sensors prepared by etch or epi etch-stop micromachining technology are already in practical use today, but the conventional bulk-Si sensor shows some drawbacks such as large chip size and limited applications as silicon sensor device is to be miniaturized. We consider a circular-shape SOI(Silicon-On-Insulator) micro-cavity technology to facilitate multiple sensors on very small chip, to make device easier to package than conventional sensor like pressure sensor and to provide very high over-pressure capability. This paper demonstrates the cross-functional results for stress analyses(targeting $5{\mu}m$ deflection and 100MPa stress as maximum at various applicable pressure ranges), for finding permissible diaphragm dimension by output sensitivity, and piezoresistive sensor theory from two-type SOI structures where the double SOI structure shows the most feasible deflection and small stress at various ambient pressures. Those results can be compared with the ones of circular-shape bulk-Si based sensor$^{[17]}. The SOI micro-cavity formed the sensors is promising to integrate with calibration, gain stage and controller unit plus high current/high voltage CMOS drivers onto monolithic chip.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.622-625
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• 2003

The dependence of stress-induced leakage current on LTPS TFTs was characterized in this study. The impacts of poly-Si crystallization, gate insulator, impurity activation, hydrogenation process and electrostatic discharge damage were investigated. It was observed more TFTs instable characteristic under those process-assisted processes. According to the LTPS roadmap, smaller geometric and low temperature process were the future trend and the stress-induced leakage current should be worthy of remark.

• Transactions on Electrical and Electronic Materials
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• 제14권5호
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• pp.250-253
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• 2013

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of $N_2$ ion implantation ($N_2$ I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage ($V_{\tau}$) of 0.13 V, and a higher $g_{m.max}$ of 18.6 ${\mu}A/V$ and mobility of 27.02 $cm^2/Vs$ than the conventional and $N_2$ I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and $N_2$ I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2006년도 추계학술대회 발표 논문집
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• pp.198-201
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• 2006

In this paper, we fabricated drag force type and pressure difference type gas flow sensor with dry etching technology which used Deep RIE(reactive ion etching) and etching stop technology which used SOI(silicon-on-insulator). we fabricated four kinds of sensor, which are cantilever, paddle type, diaphragm, and diaphragm with orifice type. Both cantilever and paddle type flow sensors have similar sensitivity as 0.03mV/V kPa. Sensitivity of the fabricated diaphragm and diaphragm with orifice type sensor were relatively high as about 3.5mV/V kPa, 1.5mV/V kPa respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권3호
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• pp.187-194
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• 2005

An analysis of the 1/f or flicker noise in FD n-channel Double Gate SOI MOSFET is proposed. In this paper, the variation of power spectral density (PSD) of the equivalent noise voltage and noise current with respect to frequency, channel length and gate-to-source voltage at various temperatures and exponent $C(i.e\;1/f^c$ is reported. The temperature is varied 125 K from to room temperature. The variation of PSD with respect to channel length down to $0.1{\mu}m$ technology is considered. It is analyzed that l/f noise in FD n-channel Double Gate SOI MOSFET is due to both carrierdensity fluctuations and mobility-fluctuations. But controversy still exits to its origin.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2006년도 추계학술대회 발표 논문집
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• pp.10-13
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• 2006

This paper describes on the fabrication and characteristics of a 3C-SiC (Silicon Carbide) micro pressure sensor for harsh environment applications. The implemented micro pressure sensor used 3C-SiC thin-films heteroepitaxially grown on SOI (Si-on-insulator) structures. This sensor takes advantages of the good mechanical properties of Si as diaphragms fabricated by D-RIE technology and temperature properties of 3C-SiC piezoresistors. The fabricated pressure sensors were tasted at temperature up to $250^{\circ}C$ and indicated a sensitivity of 0.46 mV/V*bar at room temperature and 0.28 mV/V*bar at $250^{\circ}C$. The fabricated 3C-Sic/SOI pressure sensor presents a high-sensitivity and excel lent temperature stability.

• Journal of the Optical Society of Korea
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• 제18권2호
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• pp.101-109
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• 2014

In this paper, four apodization functions are proposed for silicon-on-insulator (SOI) strip waveguides with sidewall-corrugated gratings. The effects of apodization functions on the full width at half maximum (FWHM), the side-lobe level, and the reflectivity of the reflection spectrum are studied using the coupled-mode theory (CMT) and the transfer-matrix method (TMM). The results show that applying proposed apodization functions creates very good filtering characteristics. Among investigated apodized waveguides, the apodization functions of Polynomial and z-power have the best performance in reducing side-lobes, where the side-lobe oscillations are entirely removed. Four functions are also used for precise adjustment of the bandwidth. Simulation results show that the minimum and maximum values of the FWHM are 0.74 nm and 8.48 nm respectively. In some investigated functions, changing the apodization parameters decreases the reflectivity which is compensated by increasing the grating length.