• 마이크로전자및패키징학회지
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• 제12권3호
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• pp.187-196
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• 2005

MEMS에서 제조 공정 오차 및 외부 응력은 진동형 자이로스코프와 같은 MEMS 소자의 제조 수율에 많은 영향을 미친다. 특히 비연성 진동형 자이로스코프의 경우 감지모드와 구동모드의 주파수 차의 특성은 수율에 직접적인 영향을 미친다. SOI (Silicon-On-Insulator) 공정 및 양극접합 공정으로 패키징된 자이로스코프의 경우, 노칭현상으로 인하여 구조물이 불균일하게 가공되며, 동시에 열팽창계수 차로 인하여 접합된 기판에 큰 휨이 발생한다. 그 결과주파수 차의 분포가 커지고, 동시에 수율은 저하되었다. 이를 개선하기 위하여 SiOG (Silicon On Glass) 기술을 적용하였다. SiOG 공정에서는 접합 후에 기판의 휨을 최소화 하기 위하여 1장의 실리콘 기관과 2장의 유리 기판을 사용하였으며, 노칭을 방지하기 위하여 금속 박막을 사용하였다. 그 결과 노칭 현상이 방지되었으며, 기판의 휨도 감소하였다. 또한 주파수 차의 분포도 매우 균일하게 되었으며, 주파수 차의 편차 또한 개선이 되었다. 그 결과 높은 수율 및 보다 강건한 MEMS 자이로스코프를 개발할 수 있었다.

• 한국정밀공학회지
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• 제30권1호
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• pp.128-133
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• 2013

Si Nanowire (Si-NW) arrays were fabricated by top-down method. A relatively simple method is suggested to fabricate suspended silicon nanowire arrays. This method allows for the production of suspended silicon nanowire arrays using anisotropic wet etching and conventional MEMS method of SOI (Silicon-On-Insulator) wafer. The dimensions of the fabricated nanowire arrays with the proposed method were evaluated and their effects on the Field Effect Transistor (FET) characteristics were discussed. Current-voltage (I-V) characteristics of the device with nanowire arrays were measured using a probe station and a semiconductor analyzer. The electrical properties of the device were characterized through leakage current, dielectric property, and threshold voltage. The results implied that the electrical characteristics of the fabricated device show the potential of being ion-selective field effect transistors (ISFETs) sensors.

• 한국공작기계학회논문집
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• 제11권4호
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• pp.12-18
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• 2002

Silicon on insulator(SOI) wafer is used in a variety of microsensor applications in which thermal deformations and other mechanical effects may dominate device Performance. One of major Problems associated with the manufacturing Processes of the microaccelerometer based on the tunneling current concept is thermal deformations and thermal stresses. This paper deals with finite element analysis(FEA) of residual thermal deformations causing popping up, which are induced in micrormaching processes of a microaccelerometer. The reason for this Popping up phenomenon in manufacturing processes of microaccelerometer may be the bending of the whole wafer or it may come from the way the underetching occurs. We want to seek after the real cause of this popping up phenomenon and diminish this by changing manufacturing processes of mic개accelerometer. In microaccelerometer manufacturing process, this paper intend to find thermal deformation change of the temperature distribution by tunnel gap and additional beams. The thermal behaviors analysis intend to use ANSYS V5.5.3.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.223-226
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• 2003

The EKV model, a continuous model for the MOS transistor, has been adapted to both partially depleted SOI MOSFETs with grounded body (GBSOI) and dynamic threshold MOS (DTMOS) transistors. Adaptation is straightforward and helps to understand the physics of the DTMOS. Excellent agreement is found between the model and the measured characteristics of GBSOI and DTMOS devices

• 반도체디스플레이기술학회지
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• 제3권4호
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• pp.29-32
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• 2004

Fully depleted Silicon-on-Insulator (FD-SOI) devices lead to better electrical characteristics than bulk CMOS devices. However, the presence of a thin top silicon layer and a buried SiO2 layer causes self-heating due to the low thermal conductivity of the buried oxide. The electrical characteristics of FDSOI devices strongly depend on the path of heat dissipation. In this paper, we present a new three-dimensional (3-D) analysis technique for the self-heating effect of the finger-type and bar-type transistors. The 3-D analysis results show that the drain current of the finger-type transistor is 14.7% smaller than that of the bar-type transistor due to the 3-D self-heating effect. We have learned that the rate of current degradation increases significantly when the width of a transistor is smaller that a critical value in a finger-type layout. The current degradation fro the 3-D structures of the finger-type and bar-type transistors is investigated and the design issues are also discussed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.99-100
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• 2006

Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.

• 센서학회지
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• 제15권1호
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• pp.1-6
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• 2006

We fabricated Si nano-wire MOSFET by using the conventional photolithography with a $1.5{\mu}m$ resolution. Si nano-wire was fabricated by using reactive ion etching (RIE), anisotropic wet etching and thermal oxidation on a silicon-on-insulator (SOI) substrate, and its width is 30 nm. Logarithmic circuit consisting of a NMOSFET and Si nano-wire MOSFET has been constructed for application to high-sensitivity image sensor. Its sensitivity was 1.12 mV/lux. The output voltage swing was 1.386 V.

• 센서학회지
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• 제1권2호
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• pp.131-145
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• 1992

본 논문은 SOI트랜스듀서 및 회로를 위해, Si 직접접합과 M-C국부연마법에 의한 박막SOI구조의 형성 공정을 기술한다. 또한, 이러한 박막SOI의 전기적 및 압저항효과 특성들을 SOI MOSFET와 cantilever빔으로 각각 조사했으며, bulk Si에 상당한다는 것이 확인되었다. 한편, SOI구조를 이용한 두 종류의 압력트랜스듀서를 제작 및 평가했다. SOI구조의 절연층을 압저항의 유전체분리층으로 이용한 압력트랜스듀서의 경우, $-20^{\circ}C$에서 $350^{\circ}C$의 온도범위에 있어서 감도 및 offset전압의 변화는 자각 -0.2% 및 +0.15%이하였다. 한편, 절연층을 etch-stop막으로 이용한 압력트랜스듀서에 있어서의 감도변화를 ${\pm}2.3%$의 표준편차 이내로 제어할 수 있다. 이러한 결과들로부터 개발된 SDB공정으로 제작된 SOI구조는 집적화마이크로트랜스듀서 및 회로개발에 많은 장점을 제공할 것이다.

• 소성∙가공
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• 제13권3호
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• pp.285-289
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• 2004

Micro tensile test specimens of thin film single crystal silicon for the most useful structural materials in MEMS (Micro Electro Mechanical System) devices were fabricated using SOI (Silicon-on-Insulator) wafers and MEMS processes. Dimensions of micro tensile test specimens were thickness of $7\mu\textrm{m}$, width of 50~$350\mu\textrm{m}$, and length of 2mm. Top and bottom silicon were etched using by deep RIE (Reactive Ion Etching). Thin film aluminum markers on testing region of specimens with width of $5\mu\textrm{m}$, lengths of 30~$180\mu\textrm{m}$ and thickness of 200 nm for measuring tensile strain were fabricated by aluminum wet etching method. Fabricated side wall angles of aluminum marker were about $45^{\circ}~50^{\circ}$. He-Ne laser with wavelength of 633nm was used for checking fringed patterns.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.283-284
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• 2012

In this work, a special technique called dielectric filling was carried out in order to reduce sub-threshold leakage current inside double-gated n-channel MOSFET. This calibration was done by using SILVACO Atlas(TCAD), and the result showed quite a good performance compared to the conventional double-gate MOSFET.