• 한국표면공학회지
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• 제29권5호
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• pp.482-486
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• 1996

The progress of microelectronics technology has been requiring agressive developments of device technologies. Also the requirements of the next generation devices is heading to the limits of their functions and materials, and hence asking the very specific silicon wafer such as SOI(Silicon On Insulator) wafer. The talk covers the dome stic and world-wide status of SOI device developments and applications. The presentation will also touch some predictions such as SOI device prgress schedules, impacts on the normal wafer developments, market sizes, SOI wafer prices, and so on. Finally it will cover technical aspects which are silicon oxide conditions for bonding, point defects and, surface contaminations. These points will be hopefully overcome by involved people in microelectronics industry.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2022년도 추계학술대회
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• pp.115-117
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• 2022

피드백 전계 효과 트랜지스터(feedback field-effect transistor; FBFET)로 구성된 모놀리식 3차원 정적 랜덤 액세스 메모리(monolithic 3-dimensional static random access memory; M3D-SRAM)에 대해 TCAD(technology computer-aided design) 프로그램을 사용하여 전기적 특성을 조사하였다. FBFET로 구성된 M3D-SRAM(M3D-SRAM-FBFET)는 FDSOI(fully depleted silicon on insulator) 구조의 N형 FBFET와 N형 MOSFET(metal oxide semiconductor field effect transistor)로 이루어져 있으며 각각 하부와 상부에 위치한다. M3D-SRAM-FBFET의 메모리 동작 시, 공급 전압이 1.9 V에서 감소함에 따라 읽기 전류가 낮아졌으며, 공급 전압이 1.6 V 일 때 읽기 전류가 약 10배 감소하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권3호
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• pp.183-195
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• 2007

MEMS technology is proven to be an enabling technology to realize many components for optical networking applications. Due to its widespread applications, VOA has been one of the most attractive MEMS based key devices in optical communication market. Micromachined shutters and refractive mirrors on top of silicon substrate or on the device layer of SOI (Silicon-on-insulator) substrate are the approaches trapped tremendous research activities, because such approaches enable easier alignment and assembly works. These groups of devices are known as the planar VOAs, or two-dimensional (2-D) VOAs. In this review article, we conduct the comprehensively literature survey with respect to MEMS based planar VOA devices. Apparently MEMS VOA technology is still evolving into a mature technology. MEMS VOA technology is not only the cornerstone to support the future optical communication technology, but the best example for understanding the evolution of optical MEMS technology.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2004년도 동계학술연구발표회 논문개요집
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• pp.31-32
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• 2004

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.1-11
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• 2004

A FinFET, a novel double-gate device structure is capable of scaling well into the nanoelectronics regime. High-performance CMOS FinFETs , fully depleted silicon-on-insulator (FDSOI) devices have been demonstrated down to 15 nm gate length and are relatively simple to fabricate, which can be scaled to gate length below 10 nm. In this paper, some of the key elements of these technologies are described including sub-lithographic pattering technology, raised source/drain for low series resistance, gate work-function engineering for threshold voltage adjustment as well as metal gate technology, channel roughness on carrier mobility, crystal orientation effect, reliability issues, process variation effects, and device scaling limit.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.729-732
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• 2006

The effect of stress match between silicon nitride ($SiN_2$) and hydrogenated amorphous silicon (a-Si:H) layers on the electrical characteristics of thin-film transistors (TFTs) has been investigated. The result shows that modifying the deposition conditions of a Si:H and $SiN_2$ thin films can reduce the stress mismatch at a-Si:H/SiNx interface. Moreover, for best a-Si:H TFT characteristics, the internal stress of gate $SiN_2$ layer with slightly nitrogen-rich should be matched with that of a-Si:H channel layer. The ON current, field-effect mobility, and stability of TFTs can be enhanced by controlling the stress match between a-Si:H and gate insulator. The improvement of these characteristics appears to be due to both the decrease of the interface state density between the a-Si:H and SiNx layer, and the good dielectric quality of the bottom nitride layer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.511-515
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• 2013

A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (${\sigma}$), correlation length (${\zeta}$), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e., ${\sigma}$ and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced $V_TH$ variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced $V_TH$ variation. The total random variation in $V_TH$, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).

• 센서학회지
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• 제30권6호
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• pp.395-407
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• 2021

The effect of the specifications of a silicon-on-insulator vertical slot optical waveguide on the sensitivity of homogeneous and surface sensing configurations for TE and TM polarization, respectively, was systematically analyzed using numerical software. The specifications were optimized based on the confinement factor and transmission power of the TE-guided mode distributed in the slot. The waveguide sensitivities of homogeneous and surface sensing were calculated according to the specifications of the optimized slot optical waveguide.

• 센서학회지
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• 제11권5호
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• pp.294-300
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• 2002

In this study, we fabricated thermopile infrared sensor with floating membrane structure. Floating membrane was formed by SOI(Silicon On Insulator) structure. In SOI structure, silicon dioxide layer between top silicon layer and bottom silicon substrate was etched by HF solution, then membrane was floated over substrate. After membrane was floated, thermopile pattern was formed on membrane. By insertion of SOI technology, we could obtain thermal isolation structure easily and passivation process for sensor pattern protection was not required during fabrication process. Then, the amplifier circuit for thermopile sensor was fabricated by using $1.5{\mu}m$ CMOS process. The voltage gain of fabricated amplifier was about two hundred.

• 센서학회지
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• 제16권2호
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• pp.126-131
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• 2007

In this paper, we fabricated piezoresistive pressure sensor with dry etching technology which used ICP-RIE (inductively coupled plasma reactive ion etching) and etching delay technology which used SOI (silicon-on-insulator). Structure of the fabricated pressure sensor shows a square diaphragm connected to a frame which was vertically fabricated by dry etching process and a single-element four-terminal gauge arranged at diaphragm edge. Sensitivity of the fabricated sensor was about 3.5 mV/V kPa at 1 kPa full-scale. Measurable resolution of the sensor was not exceeding 20 Pa. The nonlinearity of the fabricated pressure sensor was less than 0.5 %F.S.O. at 1 kPa full-scale.