• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.874-877
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• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• 정보학연구
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• 제8권2호
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• pp.85-91
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• 2005

We studied a pollution mechanism for simulation of contamination environment in industrial concentrated area of around a metropolitan that made to circulated flow in the chamber. In case of the virgin both side of EPDM or Silicon insulator, we confirmed that the pollution to much more than service insulator in the field. Also contamination of initial state of the virgin didn't falling in spite of physical outside factor easily. This study confirmed to that the silicon was too much accumulated pollution contrast to EPDM insulator from scatter(spray) point to regular interval position use the Kaolin contaminant in the chamber. There are effected to the hydrophobicity of polymer insulator due to the pollution. In ceramic insulator, we get to know that pollution is much more at the Post insulator with vertical than with horizontal setup insulator.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.264-275
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• 2008

Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-on-insulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.153-166
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• 2003

Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.147-152
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• 2016

In this study, we fabricated Ag-based electrochemical metallization memory devices which is also called conductive-bridge random-access memory (CBRAM) in order to investigate the resistive switching behavior depending on the bottom electrode (BE). RRAM cells of two different layer configurations having $Ag/Si_3N_4/TiN$ and $Ag/Si_3N_4/p^+$ Si are studied for metal-insulator-metal (MIM) and metal-insulator-silicon (MIS) structures, respectively. Switching voltages including forming/set/reset are lower for MIM than for MIS structure. It is found that the workfunction different affects the performances.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• 대한금속재료학회지
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• 제46권1호
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• pp.39-43
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• 2008

PSII (Plasma Source Ion Implantation) using high density pulsed ICP source was employed to implant oxygen ions in Si wafer. The PSII technique can achieve a nominal oxygen dose of $3 {\times}10^{17}atoms/cm^2$ in implantation time of about 20min. In order to prevent oxidation of SOI layer during high temperature annealing, the wafer was capped with $2,000{\AA}$ $Si_3N_4 $ by PECVD. Cross-sectional TEM showed that continuous $500{\AA}$ thick buried oxide layer was formed with $300{\AA}$ thick top silicon layer in the sample. This study showed the possibility of SOI fabrication using the plasma source ion implantation with pulsed ICP source.

• 대한기계학회논문집B
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• 제41권6호
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• pp.409-414
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• 2017

본 연구의 목적은 실제 실리콘 박막 트랜지스터 내 포논 전달 특성을 이해하는 것이다. 이를 위해 박막 소자 내 열해석 예측 정확성이 검증된 전자-포논 상호작용 모델을 이용하여 반도체 산업에서 중요한 Silicon-on-Insulator(SOI) 시스템에 대한 다양한 조건에서 전자-포논 산란에 의한 Joule 가열 메커니즘의 고려하여 포논 전달 해석을 수행했다. 소자 장치 전원(device power)과 실리콘 층 두께 변화에 따른 포논의 평균자유행로(mean free path) 스펙트럼에 대한 열적 특성을 조사하여, 실제 SOI 소자 내 포논 전달을 이해했다. 이 결과는 SOI 소자의 신뢰성 설계 및 고효율 열소산(heat dissipation) 설계전략에 필요한 포논 전달 특성 이해에 활용될 수 있다.

• 대한기계학회논문집B
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• 제40권2호
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• pp.111-117
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• 2016

본 연구의 목적은 실리콘 열전달 조절을 위한 포논의 평균자유행로(Mean free path, MFP) 스펙트럼 열전달 기여도 예측이다. 열전달의 크기 효과는 포논의 MFP 와 재료의 특성길이가 비슷할 때 나타나는데, 나노시스템 응용을 위한 재료의 열전달 증감을 위해 포논 MFP 스펙트럼에 대한 열전달 기여도 예측이 중요하다. 이를 위해 포논의 주파수 의존성이 고려된 볼츠만 수송방정식(Boltzmann transport equation) 근간의 full phonon dispersion 모델을 통해 실리콘 박막(Silicon-on-Insulator) 트랜지스터의 실리콘 박막 두께 변화(41-177 nm)에 따른 포논 MFP 스펙트럼 열전달 특성 및 비등방성을 해석함으로써, 본 연구 결과는 향후 박막 트랜지스터에 대한 고효율 열소산(heat dissipation) 설계전략에 활용될 수 있다.