Browse > Article

Electrostatic Discharge (ESD) and Failure Analysis: Models, Methodologies and Mechanisms for CMOS, Silicon On Insulator and Silicon Germanium Technologies  

Voldman, Steven H. (IBM Semiconductor Research and Research and Development Center(SRDC) Essex Junction)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.3, no.3, 2003 , pp. 153-166 More about this Journal
Abstract
Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.
Keywords
Reliability; Electrostatic; Discharge; CMOS; SOI; SiGe;
Citations & Related Records
연도 인용수 순위
  • Reference
1 B. Ronan, S.Voldman, L. Lanzerotti, J. Rascoe, D. Sheridan, and K. Rajendran, 'High Current Transmission Line Pulse (TLP) and ESD Characterization of a Silicon Germanium Heterojunction Bipolar Transistor with Carbon Incorporation,' Proceedings of the International Reliability Physics Symposium, 2002
2 R. G. Chemilli, B.A. Unger, and P.R. Bossard, 'ESD By Static Induction,' Proceedings of the EOS/ESD Symposium, pp. 29-37, 1983
3 J. Montoya, L. Levit, A. Englisch, 'A Study of Mechanisms for ESD Damage to Reticles,' Proceedings of the EOS/ESD Symposium, pp.394-405, 2000   DOI
4 A. Wallash, T. Hughbanks, and S. Voldman, 'ESD Failure Mechanisms in Inductive and Magnetoresistive Recording Heads,' Proceedings of the EOS/ESD Symposium, pp. 322-330, 1995   DOI
5 A. Wallash , J. Hillman, 'ESD Evaluation of Tunneling Magnetoresistive (TMR) Devices,' Proceedings of the EOS/ESD Symposium, pp. 470-474, 2000   DOI
6 S. Voldman, N. Schmidt, R. Johnson., L. Lanzerotti, A. Joseph, C. Brennan, J. Dunn, D. Harame, P. Juliano, E. Rosenbaum, and B. Meyerson, 'Electrostatic Discharge Characterization of Epitaxial Base Silicon Germanium Heterojunction Bipolar Transistors,' Proceedings of the EOS/ESD Symposium, pp. 239-251, Sept. 2000   DOI
7 S. Voldman et al., 'ESD Robustness of a Silicon Germanium BiCMOS Technology,' Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting Symposium, pp. 19-31, September, 2000
8 S. Voldman, L.D. Lanzerotti, and R. Johnson, 'Emitter Base Junction ESD Reliability of an Epitaxial Base Silicon Germanium Heterojunction Transistor,' Proceedings of the International Physical and Failure Analysis of Integrated Circuits, pp.79-84, July 2001   DOI
9 S. Voldman, A. Botula, D. Hui, and P. Juliano, 'Silicon Germanium Heterojunction Bipolar Transistor ESD Power Clamps and the Johnson Limit,' Proceedings of the EOS/ESD Symposium, pp. 326-336, Sept. 13, 2001
10 S. Voldman et al., 'Electrostatic Discharge and High Current Pulse Characterization of Epitaxial Base Silicon Germanium Heterojunction Bipolar Transistors,' Proceedings of the International Reliability Physics Symposium, pp.310-317, March 2000   DOI
11 S. Voldman, R. Schulz, J. Howard, V. Gross, S. Wu, A. Yapsir, D. Sadana, H. Hovel, J. Walker, F. Assaderaghi, B. Chen, J.Y.C. Sun, G. Shahidi, 'CMOS-on-SOI ESD Protection Networks,' Proceedings of the EOS/ESD Symposium, pp.291-302, 1996
12 M. Ker et al, 'Novel Diode Structures and ESD Protection Circuits in a 1.8 V 0.15 um Partially Depleted SOI Salicided CMOS Process,' Proceedings of the 9th International Physical and Failure Analysis (IPFA) Symposium, pp.91-96, Singapore, 2001   DOI
13 J. Whalen, 'The RF pulse susceptibility of UHF transistors,' IEEE Transaction of Electromagnetic Compatibility, Vol. EMC-17, pp.220-225, November 1975   DOI   ScienceOn
14 J. Whalen and H. Domingos, 'Square Pulse and RF Pulse Overstressing of UHF Transistors,' Proceedings of the EOS/ESD Symposium, pp.140-146, 1979
15 S. Voldman, J. Howard, M. Sherony, F. Assaderaghi, D. Hui, D. Young, D. Dreps, G.Shahidi, 'Silicon-On-Insulator Dynamic Threshold ESD Networks and Active Clamp Circuitry,' Proceedings of the EOS/ESD Symposium, pp.29-40, 2000   DOI
16 S. Voldman et al, 'High Current Characterization of Dual Damascene Copper/Si02 and Low-K Interlevel Dielectrics for Advanced CMOS Semiconductor Technologies,' Proceedings of the International Reliability Physics Symposium, pp.144-153, 1999
17 S. Voldman, 'Semiconductor Process and Structural Optimization of Shallow Trench Isolated-Defined and Polysilicon-Bound Source/Drain Diodes for ESD Networks,' Proceedings of the EOS/ESD Symposium, pp.151-160, 1998
18 S. Voldman et al, 'High Current Transmission Line Pulse Characterization of Aluminum and Copper Interconnects for Advanced CMOS Semiconductor Technologies,' Proceedings of the International Reliability Physics Symposium, pp.293-302, 1998   DOI
19 T. Turner, and S. Morris, 'Electrostatic Sensitivity of Various Input Protection Networks,' Proceedings of the EOS/ESD Symposium, pp.95-103, 1980
20 S. Voldman, 'ESD Robustness and Scaling Implications of Aluminum and Copper Interconnects in Advanced Semiconductor Technology,' Proceedings of the EOS/ESD Symposium, pp. 317-327, 1997
21 S. Voldman, and V. Gross, 'Scaling, Optimization, and Design Considerations of Electrostatic Discharge Protection Circuits in CMOS Technology,' Proceedings of the EOS/ESD Symposium, 1993; and Journal of Electrostatics, Vol. 33, No. 3, pp.327-357, October 1994   DOI   ScienceOn
22 S. Voldman, 'The Impact of MOSFET Technology Evolution and Scaling on Electrostatic Discharge Protection,' Microelectronics Reliability, 38, pp.1649-1668, 1998   DOI   ScienceOn
23 J. Never, and S. Voldman, 'Failure Analysis of Shallow Trench Isolated ESD Structures,' Proceedings of the EOS/ESD Symposium, pp. 273-288, 1995   DOI
24 S. Voldman, 'The Impact of Technology Evolution and Scaling on Electrostatic Discharge (ESD) Protection in High Pin Count High Performance Microprocessors,' Invited Talk, International Solid State Circuits Conference, Session 21, WA 21.4, pp. 366-367, Feb. 1999   DOI
25 K. Banerjee, 'Characterization of VLSI Circuit Interconnect Heating and Failure under ESD Conditions,' Proceedings of the International Reliability Physics Symposium, pp.237-245, 1996   DOI
26 S. Voldman, S. Furkay, and J. Slinkman, 'Three Dimensional Transient Electrothermal Simulation of Electrostatic Discharge Protection Networks,' Proceedings of the EOS/ESD Symposium, pp. 246-257, 1994
27 V. Gross and S. Voldman, 'ESD Testing and Qualification of Semiconductor Components,' Proceedings of the Electronic Component and Test Conference (ECTC) Symposium, 1996   DOI
28 S. Voldman, J. Adkisson, ' Linewidth Control Effects on MOSFET ESD Robustness,' Proceedings of the EOS/ESD Symposium, pp.101-110, 1996
29 S. Voldman, 'ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.5 and 0.25 um Channel Length CMOS Technologies,' Proceedings of the EOS/ESD Symposium, pp.125-134, 1994
30 V. M. Dwyer, A. J. Franklin, and D.S. Campbell, 'Thermal Failure in Semiconductor Devices,' pp. 553-560, Solid State Electronics, 1989   DOI   ScienceOn
31 D. Pierce and R. Mason, 'A Probabilistic Estimator for Bounding Transistor Emitter-Base Junction Transient-Induced Failures,' Proceedings of the EOS/ESD Symposium, pp.82-90, 1982
32 W.D. Brown, 'Semiconductor Device Degradation by High Amplitude Current Pulses,' IEEE Trans. On Nuclear Science, Vol. NS-19, December 1972
33 D.R. Alexander, and E.W. Enlow, 'Predicting Lower Bounds on Failure Power Distributions of Silicon NPN Transistors,' IEEE Trans. On Nuclear Science, Vol. NS-28, No.6, Dec. 1981
34 E.N. Enlow, 'Determining an Emitter-Base Failure Threshold Density of NPN Transistors,' Proceedings of the EOS/ESD Symposium, pp.145-151, 1981
35 Ash, 'Semiconductor Junction Non-linear Failure Power Thresholds: Wunsch-Bell Revisited,' Proceedings of the EOS/ESD Symposium, pp.122-127, 1983
36 V.I. Arkihpov, E. R. Astvatsaturyan, V.I. Godovosyn, and A.I. Rudenko, International Journal of Electronics, 55, p. 395, 1983   DOI   ScienceOn
37 D.C. Wunsch, and R.R. Bell, 'Determination Of Threshold Voltage Levels Of Semiconductor Diodes And Transistors Due To Pulsed Voltages,' IEEE Trans. on Nuclear Science, Vol. NS-15, No. 6, pp. 244-259, Dec. 1968
38 D. M. Tasca, 'Pulse Power Failure Modes in Semiconductors,' IEEE Trans. on Nuclear Science, NS-17, No. 6, pp. 346-372, Dec 1970