1 |
B. Ronan, S.Voldman, L. Lanzerotti, J. Rascoe, D. Sheridan, and K. Rajendran, 'High Current Transmission Line Pulse (TLP) and ESD Characterization of a Silicon Germanium Heterojunction Bipolar Transistor with Carbon Incorporation,' Proceedings of the International Reliability Physics Symposium, 2002
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A. Wallash, T. Hughbanks, and S. Voldman, 'ESD Failure Mechanisms in Inductive and Magnetoresistive Recording Heads,' Proceedings of the EOS/ESD Symposium, pp. 322-330, 1995
DOI
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5 |
A. Wallash , J. Hillman, 'ESD Evaluation of Tunneling Magnetoresistive (TMR) Devices,' Proceedings of the EOS/ESD Symposium, pp. 470-474, 2000
DOI
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6 |
S. Voldman, N. Schmidt, R. Johnson., L. Lanzerotti, A. Joseph, C. Brennan, J. Dunn, D. Harame, P. Juliano, E. Rosenbaum, and B. Meyerson, 'Electrostatic Discharge Characterization of Epitaxial Base Silicon Germanium Heterojunction Bipolar Transistors,' Proceedings of the EOS/ESD Symposium, pp. 239-251, Sept. 2000
DOI
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7 |
S. Voldman et al., 'ESD Robustness of a Silicon Germanium BiCMOS Technology,' Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting Symposium, pp. 19-31, September, 2000
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8 |
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DOI
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9 |
S. Voldman, A. Botula, D. Hui, and P. Juliano, 'Silicon Germanium Heterojunction Bipolar Transistor ESD Power Clamps and the Johnson Limit,' Proceedings of the EOS/ESD Symposium, pp. 326-336, Sept. 13, 2001
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10 |
S. Voldman et al., 'Electrostatic Discharge and High Current Pulse Characterization of Epitaxial Base Silicon Germanium Heterojunction Bipolar Transistors,' Proceedings of the International Reliability Physics Symposium, pp.310-317, March 2000
DOI
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11 |
S. Voldman, R. Schulz, J. Howard, V. Gross, S. Wu, A. Yapsir, D. Sadana, H. Hovel, J. Walker, F. Assaderaghi, B. Chen, J.Y.C. Sun, G. Shahidi, 'CMOS-on-SOI ESD Protection Networks,' Proceedings of the EOS/ESD Symposium, pp.291-302, 1996
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12 |
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15 |
S. Voldman, J. Howard, M. Sherony, F. Assaderaghi, D. Hui, D. Young, D. Dreps, G.Shahidi, 'Silicon-On-Insulator Dynamic Threshold ESD Networks and Active Clamp Circuitry,' Proceedings of the EOS/ESD Symposium, pp.29-40, 2000
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16 |
S. Voldman et al, 'High Current Characterization of Dual Damascene Copper/Si02 and Low-K Interlevel Dielectrics for Advanced CMOS Semiconductor Technologies,' Proceedings of the International Reliability Physics Symposium, pp.144-153, 1999
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17 |
S. Voldman, 'Semiconductor Process and Structural Optimization of Shallow Trench Isolated-Defined and Polysilicon-Bound Source/Drain Diodes for ESD Networks,' Proceedings of the EOS/ESD Symposium, pp.151-160, 1998
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18 |
S. Voldman et al, 'High Current Transmission Line Pulse Characterization of Aluminum and Copper Interconnects for Advanced CMOS Semiconductor Technologies,' Proceedings of the International Reliability Physics Symposium, pp.293-302, 1998
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S. Voldman, 'ESD Robustness and Scaling Implications of Aluminum and Copper Interconnects in Advanced Semiconductor Technology,' Proceedings of the EOS/ESD Symposium, pp. 317-327, 1997
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21 |
S. Voldman, and V. Gross, 'Scaling, Optimization, and Design Considerations of Electrostatic Discharge Protection Circuits in CMOS Technology,' Proceedings of the EOS/ESD Symposium, 1993; and Journal of Electrostatics, Vol. 33, No. 3, pp.327-357, October 1994
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22 |
S. Voldman, 'The Impact of MOSFET Technology Evolution and Scaling on Electrostatic Discharge Protection,' Microelectronics Reliability, 38, pp.1649-1668, 1998
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23 |
J. Never, and S. Voldman, 'Failure Analysis of Shallow Trench Isolated ESD Structures,' Proceedings of the EOS/ESD Symposium, pp. 273-288, 1995
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24 |
S. Voldman, 'The Impact of Technology Evolution and Scaling on Electrostatic Discharge (ESD) Protection in High Pin Count High Performance Microprocessors,' Invited Talk, International Solid State Circuits Conference, Session 21, WA 21.4, pp. 366-367, Feb. 1999
DOI
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25 |
K. Banerjee, 'Characterization of VLSI Circuit Interconnect Heating and Failure under ESD Conditions,' Proceedings of the International Reliability Physics Symposium, pp.237-245, 1996
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26 |
S. Voldman, S. Furkay, and J. Slinkman, 'Three Dimensional Transient Electrothermal Simulation of Electrostatic Discharge Protection Networks,' Proceedings of the EOS/ESD Symposium, pp. 246-257, 1994
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27 |
V. Gross and S. Voldman, 'ESD Testing and Qualification of Semiconductor Components,' Proceedings of the Electronic Component and Test Conference (ECTC) Symposium, 1996
DOI
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28 |
S. Voldman, J. Adkisson, ' Linewidth Control Effects on MOSFET ESD Robustness,' Proceedings of the EOS/ESD Symposium, pp.101-110, 1996
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29 |
S. Voldman, 'ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.5 and 0.25 um Channel Length CMOS Technologies,' Proceedings of the EOS/ESD Symposium, pp.125-134, 1994
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30 |
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34 |
E.N. Enlow, 'Determining an Emitter-Base Failure Threshold Density of NPN Transistors,' Proceedings of the EOS/ESD Symposium, pp.145-151, 1981
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35 |
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