• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.874-877
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• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• The Journal of Information Technology
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• v.8 no.2
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• pp.85-91
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• 2005

We studied a pollution mechanism for simulation of contamination environment in industrial concentrated area of around a metropolitan that made to circulated flow in the chamber. In case of the virgin both side of EPDM or Silicon insulator, we confirmed that the pollution to much more than service insulator in the field. Also contamination of initial state of the virgin didn't falling in spite of physical outside factor easily. This study confirmed to that the silicon was too much accumulated pollution contrast to EPDM insulator from scatter(spray) point to regular interval position use the Kaolin contaminant in the chamber. There are effected to the hydrophobicity of polymer insulator due to the pollution. In ceramic insulator, we get to know that pollution is much more at the Post insulator with vertical than with horizontal setup insulator.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.264-275
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• 2008

Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-on-insulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.153-166
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• 2003

Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.147-152
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• 2016

In this study, we fabricated Ag-based electrochemical metallization memory devices which is also called conductive-bridge random-access memory (CBRAM) in order to investigate the resistive switching behavior depending on the bottom electrode (BE). RRAM cells of two different layer configurations having $Ag/Si_3N_4/TiN$ and $Ag/Si_3N_4/p^+$ Si are studied for metal-insulator-metal (MIM) and metal-insulator-silicon (MIS) structures, respectively. Switching voltages including forming/set/reset are lower for MIM than for MIS structure. It is found that the workfunction different affects the performances.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• Korean Journal of Metals and Materials
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• v.46 no.1
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• pp.39-43
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• 2008

PSII (Plasma Source Ion Implantation) using high density pulsed ICP source was employed to implant oxygen ions in Si wafer. The PSII technique can achieve a nominal oxygen dose of $3 {\times}10^{17}atoms/cm^2$ in implantation time of about 20min. In order to prevent oxidation of SOI layer during high temperature annealing, the wafer was capped with $2,000{\AA}$ $Si_3N_4 $ by PECVD. Cross-sectional TEM showed that continuous $500{\AA}$ thick buried oxide layer was formed with $300{\AA}$ thick top silicon layer in the sample. This study showed the possibility of SOI fabrication using the plasma source ion implantation with pulsed ICP source.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.41 no.6
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• pp.409-414
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• 2017

The aim of this study is to understand the phonon transfer characteristics of a silicon thin film transistor. For this purpose, the Joule heating mechanism was considered through the electron-phonon interaction model whose validation has been done. The phonon transport characteristics were investigated in terms of phonon mean free path for the variations in the device power and silicon layer thickness from 41 nm to 177 nm. The results may be used for developing the thermal design strategy for achieving reliability and efficiency of the silicon-on-insulator (SOI) transistor, further, they will increase the understanding of heat conduction in SOI systems, which are very important in the semiconductor industry and the nano-fabrication technology.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.2
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• pp.111-117
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• 2016

The primary concern of this research is to examine the phonon mean free path (MFP) spectrum contribution to heat conduction. The size effect of materials is determined by phonon MFP, and the size effect appears when the phonon MFP is similar to or less than the characteristic length of materials. Therefore, knowledge of the phonon MFP is essential to increase or decrease the heat conduction of a material for engineering applications, such as micro/nanosystems. In this study, frequency dependence of the phonon transport is considered using the Boltzmann transport equation based on a full phonon dispersion model. Additionally, the phonon MFP spectrums of in-plane and out-of-plane heat transport are investigated by varying the film thickness of the silicon layer from 41 nm to 177 nm. This will increase the understanding of anisotropic heat conduction in a SOI (Silicon-on-Insulator) transistor.