• 반도체디스플레이기술학회지
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• 제2권2호
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• pp.9-15
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• 2003

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12" silicon wafer for spin etcher. Halogen lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and adaptive filtering. Test wafers with three kinds of priori-known films, polysilicon(300 nm), silicon-oxide(500 nm) and silicon-oxide(600 nm), are measured while the wafer is spinning at 20 Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 0.8% error.rror.

• 전기학회논문지
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• 제60권7호
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• pp.1434-1437
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• 2011

Precision measurement of silicon wafer resistivity has been using single-configuration Four-Point Probe(FPP) method. This FPP method have to applying sample size, shape and thickness correction factor for a probe pin spacing to precision measurement of silicon wafer. The deference for resistivity measurement values applied correction factor and not applied correction factor was about 1.0 % deviation. The sample size, shape and thickness correction factor for a probe pin spacing have an effects on precision measurement for resistivity of silicon wafer.

• 한국주조공학회지
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• 제33권4호
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• pp.157-161
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• 2013

A ribbon-type polycrystalline silicon wafer was directly fabricated from liquid silicon via a novel technique for both a fast growth rate and large grain size by exploiting gas pressure. Effects of processing parameters such as moving speed of a dummy bar and the length of the solidification zone on continuous casting of the silicon wafer were investigated. Silicon melt extruded from the growth region in the case of a solidification zone with a length of 1cm due to incomplete solidification. In case of a solidification zone wieh a length of 2 cm, on the other hand, continuous casting of the wafer was impossible due to the volume expansion of silicon derived from the liquid-solid transformation in solidification zone. Consequently, the optimal length of the solidification zone was 1.5 cm for maintaining the position of the solid-liquid interface in the solidification zone. The silicon wafer could be continuously casted when the moving speed of the dummy bar was 6 cm/min, but liquid silicon extruded from the growth region without solidification when the moving speed of the dummy bar was ${\geq}$ 9 cm/min. This was due to a shift of the position of the solid-liquid interface from the solidification zone to the moving area. The present study reports experimental findings on a new direct growth system for obtaining silicon wafers with both high quality and productivity, as a candidate for an alternate route for the fabrication of ribbon-type silicon wafers.

• 한국정밀공학회지
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• 제27권2호
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• pp.13-19
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• 2010

Due to the rapid spread of mobile handheld devices, industrial demands for micro-scale holes with a diameter of even smaller than $10{\mu}m$ in sapphire/silicon wafers have been increasing. Holes in sapphire wafers are for heat dissipation from LEDs; and those in silicon wafers for interlayer communication in three-dimensional integrated circuit (IC). We have developed a sapphire wafer driller equipped with a 532nm laser in which a cooling chuck is employed to minimize local heat accumulation in wafer. Through the optimization of process parameters (pulse energy, repetition rate, number of pulses), quality holes with a diameter of $30{\mu}m$ and a depth of $100{\mu}m$ can be drilled at a rate of 30holes/sec. We also have developed a silicon wafer driller equipped with a 355nm laser. It is able to drill quality through-holes of $15{\mu}m$ in diameter and $150{\mu}m$ in depth at a rate of 100holes/sec.

• 한국신뢰성학회지:신뢰성응용연구
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• 제16권1호
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• pp.26-31
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• 2016

Purpose: The purpose of this study was to investigate the effect of grinding process and thickness on the fracture strength of silicon die used for semiconductor substrate. Method: Silicon wafers with different thickness from $200{\mu}m$ to $50{\mu}m$ were prepared by chemical mechanical polishing (CMP) and dicing before grinding (DBG) process, respectively. Fracture load was measured by point load test for 50 silicon dies per each wafer. Results: Fracture strength at the center area was lower than that at the edge area of the wafer fabricated by DBG process, while random distribution of the fracture strength was observed for the CMPed wafer. Average fracture strength of DBGed specimens was higher than that of the CMPed ones for the same thickness of wafer. Conclusion: DBG process can be more helpful for lowering fracture probability during the semiconductor fabrication process than CMP process.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2000년도 추계학술대회논문집B
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• pp.261-266
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• 2000

Temperature variation during silicon wafer baking is mainly due to natural convection caused by temperature difference between silicon wafer and upper plate. Several cases are tested and calculated numerically to improve temperature uniformity. The temperature difference and velocity magnitude in the flow cell is reduced for a small gap between the wafer and upper plate because the natural convection force is suppressed in the small space. The uniform temperature distribution can be obtained with controling the incoming flow distribution from the upper plate. An alternative method is the adiabatic wall condition on the upper plate to maintain the temperature uniformity within $0.3^{\circ}C$ on the water plate.

• 한국재료학회지
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• 제15권5호
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• pp.313-317
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• 2005

The relation between bulk microdefect (BMD) and mechanical strength of $P/P^-$ epitaxial silicon wafers (Epitaxial wafer) as a function of nitrogen concentrations was studied. After 2 step anneal$(800^{\circ}C/4hrs+1000^{\circ}C/16hrs)$, BMD was not observed in nitrogen undoped epitaxial silicon wafer while BMD existed and increased up to $3.83\times10^5\;ea/cm^2$ by addition of $1.04\times10^{14}\;atoms/cm^3$ nitrogen doping. The slip occurred for nitrogen undoped and low level nitrogen doped epitaxial wafers. However, there was no slip occurrence above $7.37\times10^{13}\;atoms/cm^3$ nitrogen doped epitaxial wafer. Mechanical strength was improved from 40 to 57 MPa as nitrogen concentrations were increased. Therefore, the nitrogen doping in silicon wafer plays an important role to improve BMD density, slip occurrence and mechanical strength of the epitaxial silicon wafers.

• The Korean Journal of Ceramics
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• 제3권1호
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• pp.18-20
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• 1997

The fabrication process of silicon-diamond(SOD) structure wafer were studied. Microwave plasma chemical vapor deposition (MWPCVD) and annealing technology were used to synthesize diamond film with high resistivity and thermal conductivity. Bonding and etchback silicon-on-diamond (BESOD) were utilized to form supporting substrate and single silicon thin layer of SOD wafer. At last, a SOD structure wafer with 0.3~1$\mu\textrm{m}$ silicon film and 2$\mu\textrm{m}$ diamond film was prepared. The characteristics of radiation for a CMOS integrated circuit (IC) fabricated by SOD wafer were studied.

• 한국재료학회지
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• 제23권6호
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• pp.316-321
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• 2013

The electrical properties and surface morphology changes of a silicon wafer as a function of the HF concentration as the wafer is etched were studied. The HF concentrations were 28, 30, 32, 34, and 36 wt%. The surface morphology changes of the silicon wafer were measured by an SEM ($80^{\circ}$ tilted at ${\times}200$) and the resistivity was measured by assessing the surface resistance using a four-point probe method. The etching rate increased as the HF concentration increased. The maximum etching rate 27.31 ${\mu}m/min$ was achieved at an HF concentration of 36 wt%. A concave wave formed on the wafer after the wet etching process. The size of the wave was largest and the resistivity reached 7.54 $ohm{\cdot}cm$ at an 30 wt% of HF concentration. At an HF concentration of 30 wt%, therefore, a silicon wafer should have good joining strength with a metal backing as well as good electrical properties.

• 한국주조공학회지
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• 제33권2호
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• pp.69-74
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• 2013

Silicon (Si) wafer was grown by using direct growth from Si melt and contaminations of wafer during the process were investigated. In our process, BN was coated inside of all graphite parts including crucible in system to prevent carbon contamination. In addition, coated BN layer enhance the wettability, which ensures the favorable shape of grown wafer by proper flow of Si melt in casting mold. As a result, polycrystalline silicon wafer with dimension of $156{\times}156$ mm and thickness of $300{\pm}20$ um was successively obtained. There were, however, severe contaminations such as BN and SiC on surface of the as-grown wafer. While BN powders were easily removed by brushing surface, SiC could not be eliminated. As a result of BN analysis, C source for SiC was from binder contained in BN slurry. Therefore, to eliminate those C sources, additional flushing process was carried out before Si was melted. By adding 3-times flushing processes, SiC was not detected on the surface of as-grown Si wafer. Polycrystalline Si wafer directly grown from Si melt in this study can be applied for the cost-effective Si solar cells.