• The Korean Journal of Ceramics
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• v.3 no.1
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• pp.18-20
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• 1997

The fabrication process of silicon-diamond(SOD) structure wafer were studied. Microwave plasma chemical vapor deposition (MWPCVD) and annealing technology were used to synthesize diamond film with high resistivity and thermal conductivity. Bonding and etchback silicon-on-diamond (BESOD) were utilized to form supporting substrate and single silicon thin layer of SOD wafer. At last, a SOD structure wafer with 0.3~1$\mu\textrm{m}$ silicon film and 2$\mu\textrm{m}$ diamond film was prepared. The characteristics of radiation for a CMOS integrated circuit (IC) fabricated by SOD wafer were studied.

• 한국신재생에너지학회:학술대회논문집
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• 2009.06a
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• pp.172-175
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• 2009

n-type crystalline silicon wafers were passivated with intrinsic a-Si:H thin films on both sides using HWCVD. Minority carrier lifetime measurement was used to verify interface passivation properties between a-Si:H thin film and crystalline Si wafer. Thin film interface characteristics were investigated depending on $H_2/SiH_4$ ratio and hot wire deposition temperature. Vacuum annealing were processed after deposition a-Si:H thin films on both sides to investigate thermal effects from post process steps. We noticed the effect of interface passivation properties according to $H_2/SiH_4$ ratio and hot wire deposition temperature, and we had maximum point of minority carrier lifetime at H2/SiH4 10 ratio and $1600^{\circ}C$ wire temperature.

• 한국태양에너지학회:학술대회논문집
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• 2012.03a
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• pp.108-112
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• 2012

Crystalline silicon solar cell remains the major player in the photovoltaic marketplace with 90 % of the market, despite the development of a variety of thin film technologies. Silicon's excellent efficiency, stability, material abundance and low toxicity have helped to maintain its position of dominance. However, the cost of silicon photovoltaic remains a major barrier to reducing the cost of silicon photovoltaics. Using the crystalline silicon wafer with thinner thickness is the promising way for cost and material reduction in the solar cell production. However, the thinner thickness of silicon wafer is, the worse bow phenomenon is induced. The bow phenomenon is observed when two or more layers of materials of different temperature expansion coefficiencies are in contact, in this case silicon and aluminum. In this paper, the solar cells were fabricated with different thicknesses of Al layer in order to reduce the bow phenomenon. With lower paste applications, we observed that the bow could be reduced by up to 40% of the largest value with 130 micron thickness of the wafer even though the conversion efficiency decrease of 0.5 % occurred. Since the bowed wafers lead to unacceptable yield losses during the module construction, the reduction of bow is indispensable on thin crystalline silicon solar cell. In this work, we have studied on the counterbalance between the bow and conversion efficiency and also suggest the formation of enough back surface field (BSF) with thinner Al paste application.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.3
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• pp.134-142
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• 1995

We discovered that each distinct shape of the roof-shaped peaks of (111) facets, which are generated on (110) cross-section of the directly bonded (100) silicon wafer pairs after KOH etching, can be mapped to one of three conditions of the interfacial oxide existing at the bonding interface as follows. That is, thick solid line can be mapped to stabilization, thin solid line to disintegration, and thin broken line to spheroidization. also we confirmed that most of the interfacial oxides of a well-aligned wafer pairs were disintegrated and spheroidized through high-temperature annealing process above 900$^{\circ}$C while the oxide was stabilized persistently when two wafers are bonded rotationally around their common axis perpendicular to the wafer planes.

• Journal of the Korean Ceramic Society
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• v.36 no.8
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.

• Journal of Integrative Natural Science
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• v.3 no.4
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• pp.219-225
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• 2010

On the surface of mesoporous silica thin films (MSTF) which were fabricated by sol-gel approach there are existences of water and three different silanol types including chained, germinal and isolated silanol. Their amounts changes as a function of aging time of used sol solution, as confirmed by FT-IR. The adsorbed water generates ionic carriers such as H+ and OH- and passivates the Si dangling bonds at the interface of silicon wafer-MSTF. The ionic carriers can not only transport across the thickness of thin film to enhance the leakage current but also diffuse toward the silicon wafer-MSTF interface to depassivate Si dangling bonds. On the other hand, chained silanols or germinal silanols promote the moisture adsorption of MSTF and tend to form strongly hydrogen bonded systems with adsorbed water molecules resulting in very high dielectric constant. Isolated silanol, on the contrary, affects less on electrical properties of thin film.

• Journal of Industrial and Engineering Chemistry
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• v.67
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• pp.417-428
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• 2018

In this study, we fabricated hierarchically self-assembled thin films composed of graphene oxide (GO) sheets and gold nanoparticles (Au NPs) using the Langmuir-Blodgett (LB) and Langmuir-Schaefer (LS) techniques and investigated their gas-sensing performance. First, a thermally oxidized silicon wafer ($Si/SiO_2$) was hydrophobized by depositing the LB films of cadmium arachidate. Thin films of ligand-capped Au NPs and GO sheets of the appropriate size were then sequentially transferred onto the hydrophobic silicon wafer using the LB and the LS techniques, respectively. Several different films were prepared by varying the ligand type, film composition, and surface pressure of the spread monolayer at the air/water interface. Their structures were observed by scanning electron microscopy (SEM) and atomic force microscopy (AFM), and their gas-sensing performance for $NH_3$ and $CO_2$ was assessed. The thin films of dodecanethiol-capped Au NPs and medium-sized GO sheets had a better hierarchical structure with higher uniformity and exhibited better gas-sensing performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.42-45
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• 1992

The poly silicon thin films were prepared by solid phase crystallization at 600$^{\circ}C$ of amorphous silicon films deposited on Corning 7059 glass and (100) silicon wafer with thermally grown SiO$_2$substrate by plasma enhanced chemical vapor deposition with varying rf power, deposition temperature, total flow rate. Crystallization time, microstructure, absorption coefficients were investigated by RAMAN, XRD analysis and UV transmittance measurement. Crystallization time of amorphous silicon films was increased with increasing rf power, decreasing deposition temperature and decreasing total flow rate.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.969-974
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• 2003

A simple and cost-effective method for the electrostatic suspension of thin plates like silicon wafers is proposed which is based on a switched voltage control scheme. It operates according to a relay feedback control and deploys only a single high-voltage power supply that can deliver a dc voltage of positive and/or negative polarity. This method possesses the unique feature that no high-voltage amplifiers are needed which leads to a remarkable system simplification relative to conventional methods. It is shown that despite the inherent limit cycle property of the relay feedback based control, an excellent performance in vibration suppression is attained due to the presence of a relatively large squeeze film damping origination from the air between the electrodes and levitated object. Using this scheme, a 4-inch silicon wafer was levitated stably with airgap variation decreasing down to 1 $\mu\textrm{m}$ at an airgap of 100 $\mu\textrm{m}$

• Journal of the Korean Society for Precision Engineering
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• v.22 no.10 s.175
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• pp.56-64
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• 2005

A simple and cost-effective method for the electrostatic suspension of thin plates like silicon wafers is proposed which is based on a switched voltage control scheme. It operates according to a relay feedback control and deploys only a single high-voltage power supply that can deliver a DC voltage of positive and/or negative polarity. This method possesses the unique feature that no high-voltage amplifiers are needed which leads to a remarkable system simplification relative to conventional methods. It is shown that despite the inherent limit cycle property of the relay feedback based control, an excellent performance in vibration suppression is attained due to the presence of a relatively large squeeze film damping origination from the air between the electrodes and levitated object. Using this scheme, a 4-inch silicon wafer was levitated stably with airgap variation decreasing down to $1 {\mu}m$ at an airgap of $100{\mu}m$.