• Journal of the Korean Solar Energy Society
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• 제33권2호
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• pp.11-17
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• 2013

Silicon nitride($SiN_x:H$) deposited by radio frequency plasma enhanced chemical vapor deposition(RF-PECVD) is commonly used for anti-reflection coating and passivation in crystalline silicon solar cell fabrication. In this paper, characteristics of the deposited silicon nitride was studied with change of working pressure, deposition temperature, gas ratio of $NH_3$ and $SiH_4$, and RF power during deposition. The deposition rate, refractive index and effective lifetime were analyzed. The (100) p-type silicon wafers with one-side polished, $660-690{\mu}m$, and resistivity $1-10{\Omega}{\cdot}cm$ were used. As a result, when the working pressure increased, the deposition rate of SiNx was increased while the effective life time for the $SiN_x$-deposited wafer was decreased. The result regarding deposition temperature, gas ratio and RF power changes would be explained in detail below. In this paper, the optimized condition in silicon nitride deposition for silicon solar cell was obtained as 1.0 Torr for the working pressure, $400^{\circ}C$ for deposition temperature, 500 W for RF power and 0.88 for $NH_3/SiH_4$ gas ratio. The silicon nitride layer deposited in this condition showed the effective life time of > $1400{\mu}s$ and the surface recombination rate of 25 cm/s. The crystalline silicon solar cell fabricated with this SiNx coating showed 18.1% conversion efficiency.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제29권8호
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• pp.455-460
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• 2016

A textured front surface is required in high efficiency silicon solar cells to reduce reflectance and to improve light trapping. Wet etching with alkaline solution is usually applied for mono crystalline silicon solar cells. However, alkali texturing method is not appropriate for multi-crystalline silicon wafers due to grain boundary of random crystallographic orientation. Accordingly, acid texturing method is generally used for multi-crystalline silicon wafers to reduce the surface reflectance. To reduce reflectivity of multi-crystalline silicon wafers, double texturing method with combination of acid and reactive ion etching is an attractive technical solution. In this paper, we have studied to optimize RIE condition by different RF power condition (100, 150, 200, 250, 300 W).

• Proceedings of the KIEE Conference
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1462-1463
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• 2008

패키징 재료로 유연성이 뛰어난 polydimethyl-siloxane (PDMS)를 사용하면 다양한 flexible packaging에 응용할 수 있다. 본 논문에서는 $O_2$ plasma를 이용한 PDMS의 표면 처리를 통해 PDMS의 표면에너지를 증가시키고, silicon과 PDMS 사이의 접착력 향상을 확인하였다. $O_2$ plasma power와 처리 시간에 따른 PDMS 표면의 접촉각을 측정하고 표면에너지를 산출하였는데, PDMS의 표면에너지는 $O_2$ plasma power에는 크게 영향을 받지 않고, plasma 처리 시간에 민감한 것으로 나타났다. Silicon-PDMS의 접착력 역시 plasma power에는 거의 영향을 받지 않았지만 plasma 처리 시간이 길어질수록 접착력이 커지는 것으로 확인되었는데 50W의 power로 25초 동안 처리한 조건에서 최대 130kPa의 압력까지 견디는 것으로 확인되었다. 이는 $O_2$ plasma 처리 시간이 길어짐에 따라 PDMS의 표면에너지가 커지고 이것이 silicon-PDMS의 접착력을 증가시키는 것을 나타낸다.

• Journal of Power Electronics
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• 제19권4호
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• pp.1054-1067
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• 2019

This paper systematically investigates the influence of device parameters spread on the current distribution of paralleled silicon carbide (SiC) MOSFETs. First, a variation coefficient is introduced and used as the evaluating norm for the parameters spread. Then a sample of 30 SiC MOSFET devices from the same batch of a well-known company is selected and tested under the same conditions as those on datasheet. It is found that there is big difference among parameters spread. Furthermore, comprehensive theoretical and simulation analyses are carried out to study the sensitivity of the current imbalance to variations of the device parameters. Based on the concept of the control variable method, the influence of each device parameter on the steady-state and transient current distributions of paralleled SiC MOSFETs are verified separately by experiments. Finally, some screening suggestions of devices or chips before parallel-connection are provided in terms of different applications and different driver configurations.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2011년도 추계학술발표대회 논문집
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• pp.27-33
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• 2011

HCPV(High Concentrated PV) systems have well known for CPV market all over the world. Low concentration type silicon based modules have been introduced in the market. But low cost of standard flat silicon modules made them useless nowadays. High cost of compound semiconductor solar cell reduced cost effective cpv module production than that of recently silicon solar cell. In order to overcome increasing cost of CPV module, we study middle concentration type fresnel lens simulation using concentrated type silicon based solar cell. Linear type fresnel lens made production of CPV module without secondary optics such as light pipe or light tunnel. This type of fresnel lens design makes more cost effective solution for cpv niche market.

• Journal of Information Display
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• 제11권1호
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• pp.21-23
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• 2010

A new level shifter using low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) for low-power applications is proposed. The proposed level shifter uses a capacitive-coupling effect and can reduce the power consumption owing to its no-short-circuit current. Its power saving over the conventional level shifter is 72% for a 3.3 V input and a 10 V output.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.3-6
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• 2004

Power semiconductor devices are being compact, high performance and intelligent thanks to recent remarkable developments of silicon design, process and related packaging technologies. Developments of MOS-gate transistors such as MOSFET and IGBT are dominant thanks to their advantages on high speed operation. In conjunction with package technology, silicon technologies such as trench, charge balance and NPT will support future power semiconductors. In addition, wide band gap material such as SiC and GaN are being studies for next generation power semiconductor devices.

• Electronic Materials Letters
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• 제14권6호
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• pp.718-724
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• 2018

With the development of photovoltaic industry, the cost of photovoltaic power generation has become the significant issue. And the metallization process has decided the cost of original materials and photovoltaic efficiency of the solar cells. Nowadays, double printing process has been introduced instead of one-step printing process for front contact of polycrystalline silicon solar cells, which can effectively improve the photovoltaic conversion efficiency of silicon solar cells. Here, the relative cheap Cu paste has replaced the expensive Ag paste to form Ag/Cu composite front contact of silicon solar cells. The photovoltaic performance and the cost of photovoltaic power generation have been investigated. With the optimization on structure and height of Cu finger layer for Ag/Cu composite double-printed front contact, the silicon solar cells have exhibited a photovoltaic conversion efficiency of 18.41%, which has reduced 3.42 cent per Watt for the cost of photovoltaic power generation.

• Journal of Power System Engineering
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• 제5권4호
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• pp.11-17
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• 2001

Micronization of sensor is a trend of the silicon sensor development with regard to a piezoresistive silicon pressure sensor, the size of the pressure sensor diaphragm have become smaller year by year, and a microaccelerometer with a size less than $200{\sim}300{\mu}m$ has been realized, In this paper, we study some of the bonding processes of SCS(single crystal silicon) insulator wafer for the microaccelerometer. and their subsequent processes which might affect thermal loads. The finite element method(FEM) has been a standard numerical modeling technique extensively utilized in micro structural engineering discipline for design of SCS insulator wafers. Successful temperature distribution analysis and design of the SCS insulator wafers based on the tunneling current concept using microaccelerometer depend on the knowledge about normal mechanical properties of the SCS and $SiO_2$ layer and their control through manufacturing processes.

• Journal of Electrical Engineering and Technology
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• 제9권4호
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• pp.1343-1348
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• 2014

The low frequency noise in Silicon Nanowire Field Effect Transistors is analyzed by characterizing the gate electrode dependence on various geometrical parameters. It shows that gate electrodes have a strong impact in the flicker noise of Silicon Nanowire Field effect transistors. Optimization of gate electrode was done by comparing different performance metrics such a DIBL, SS, $I_{on}/I_{off}$ and fringing capacitance using TCAD simulations. Molybdenum based gate electrode showed significant improvement in terms of high drive current, Low DIBL and high $I_{on}/I_{off}$. The noise power sepctral density is reduced by characterizing the device at higher frequencies. Silicon Nanowire with Si3N4 spacer decreases the drain current spectral density which interms reduces the fringing fields there by decreasing the flicker noise.