• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.35T no.1
• /
• pp.29-32
• /
• 1998

The low level leakage currents in silicon oxides were investigated. The low level leakage currents were composed of a transient component and a do component. The transient component was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The do component was caused by trap assisted tunneling completely through the oxide. The low level leakage current was proportional to the number of traps generated in the oxides. The low level leakage current may be a trap charging and discharging current. The low level leakage current will affect data retention in EEPROM.

• Journal of the Korean Ceramic Society
• /
• v.31 no.7
• /
• pp.777-783
• /
• 1994

Oxidation behavior of hot-pressed silicon nitride ceramics with various sintering additives has been investigated. The weight gain of each specimens has shown in the range of 0.11 mg/$\textrm{cm}^2$ ~3.4 mg/$\textrm{cm}^2$ at 140$0^{\circ}C$ for 192 h and eleven compositions have shown good oxidation resistance with the weight gain below 0.5 mg/$\textrm{cm}^2$. The oxidation rate has been shown to obey the parabolic rate law and the oxidized surface has consisted of $\alpha$-cristobalite and M2Si2O7 or MSiO3 (M=rare earth or transition metals) phase. The oxidation rate of each specimens has related to the eutectic temperature between additive oxide and SiO2, and ionic radius of additive oxides, respectively. From the above results, it could be concluded that the oxidation behavior of hot pressed silicon nitride is dominated by the high temperature properties of grain boundary glassy phase and the high temperature properties of grain boundary glassy phase are affected by the ionic radius of additive oxides.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.05a
• /
• pp.252-254
• /
• 2002

Metal oxides with high dielectric constants have the potential to expend scaling of transistor gate capacitance beyond that of ultrathin silicon dioxide. However, during deposition of most metal oxides on silicon, an interfacial region of SiOx is formed and limits the specific capacitance of the gate structure. We deposisted aluminum oxide and examined the composition of the interfacial layer by employing high-resolution X-ray photoelectron spectroscopy and X-ray reflectivity. We find that the interfacial region is not pure SiO$_2$, but is composed of a complex depth-dependent ternary oxide of $AlSi_xO_y$ and the pure SiO$_2$.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.39 no.4
• /
• pp.335-340
• /
• 2002

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4${\AA}$ and 814${\AA}$, which have the gate area $10^3cm^2$. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.366.1-366.1
• /
• 2014

The rare-earth oxides M2O3 (M=La, Pr, Gd) are good insulators due to their large band gap (3.9eV for Pr2O3, 5.6eV for Gd2O3), they have high dielectric constants (Gd2O3 K=16, La2O3 K=27, Pr2O3 K=26-30) and, compared to ZrO2 and HfO2, they have higher thermodynamic stability on silicon making them very attractive materials for high-K dielectric applications. Another attractive feature of some rare-earth oxides is their relatively close lattice match to that of silicon, offering the possibility of epitaxial growth and eliminating problems related to grain boundaries in polycrystalline films. Metal-organic chemical vapor deposition (MOCVD) has been preferred to PVD methods because of the possibility of large area deposition, good composition control and excellent conformal step coverage. Herein we report on the synthesis of rare-earth oxide complexes with designed alkoxide and aminoalkoxide ligand. These novel complexes have been characterized by means of FT-IR, elemental analysis, and thermogravimetric analysis (TGA).

• Metals and materials international
• /
• v.24 no.6
• /
• pp.1394-1402
• /
• 2018

This study investigates the mechanism of MnS precipitation on $Al_2O_3-SiO_2$ inclusions during the solidification of non-oriented silicon steel, especially the influence of the phase structures and sizes of the oxides on the MnS precipitation, by scanning electron microscopy and transmission electron microscopy coupled with energy dispersive spectrometry. The investigation results show that MnS tends to nucleate on submicron-sized $Al_2O_3-SiO_2$ inclusions formed by interdendritic segregation and that it covers the oxides completely. In addition, MnS can precipitate on micron-sized oxides and its precipitation behavior is governed by the phase structure of the oxides. The MnS embryo formed in a MnO-containing oxide can act as a substrate for MnS precipitation, thus permitting further growth via diffusion of solute atoms from the matrix. MnS also precipitates in a MnO-free oxide by the heterogeneous nucleation mechanism. Furthermore, MnS is less prone to precipitation in the $Al_2O_3$-rich regions of the $Al_2O_3-SiO_2$ inclusions; this can be explained by the high lattice disregistry between MnS and $Al_2O_3$.

• Journal of the Korean Society for Precision Engineering
• /
• v.16 no.3 s.96
• /
• pp.78-83
• /
• 1999

The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.05a
• /
• pp.461-464
• /
• 1999

This study has been investigated that traps generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The charge state of the traps can easily be changed by application of low voltages after the stress high voltage. These trap generation involve either electron impact ionization processes or high field generation processes. It determined to the relative traps locations inside the oxides ranges from 113.4$\AA$ to 814$\AA$ with capacitor areas of 10$^{-3}$ $\textrm{cm}^2$ . The oxide charge state of traps generated by the stress high voltage contain either a positive or a negative charge.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.20 no.4
• /
• pp.395-400
• /
• 2011

Scanning Probe Lithography is a method to localized oxidation on single crystal silicon wafer surface. This study demonstrates nanometer scale non contact lithography process on (100) silicon (p-type) wafer surface using AFM(Atomic force microscope) apparatuses and pulse controlling methods. AFM-based experimental apparatuses are connected the DC pulse generator that supplies ultra short pulses between conductive tip and single crystal silicon wafer surface maintaining constant humidity during processes. Then ultra short pulse durations are controlled according to various experimental conditions. Non contact lithography of using ultra short pulse induces electrochemical reaction between micro-scale tip and silicon wafer surface. Various growths of oxides can be created by ultra short pulse non contact lithography modification according to various pulse durations and applied constant humidity environment.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.8 no.1
• /
• pp.25-32
• /
• 2007

We investigated the silicide reaction stability between 10 nm-Col-xNix alloy films and silicon substrates with the existence of 4 nm-thick natural oxide layers. We thermally evaporated 10 nm-Col-xNix alloy films by varying $x=0.1{\sim}0.9$ on naturally oxidized single crystal and 70 nm-thick polycrystalline silicon substrates. The films structures were annealed by rapid thermal annealing (RTA) from $600^{\circ}C$ to $1100^{\circ}C$ for 40 seconds with the purpose of silicidation. After the removal of residual metallic residue with sulfuric acid, the sheet resistance, microstructure, composition, and surface roughness were investigated using a four-point probe, a field emission scanning electron microscope, a field ion bean4 an X-ray diffractometer, and an Auger electron depth profiling spectroscope, respectively, to confirm the silicide reaction. The residual stress of silicon substrate was also analyzed using a micro-Raman spectrometer We report that the silicide reaction does not occur if natural oxides are present. Metallic oxide residues may be present on a polysilicon substrate at high silicidation temperatures. Huge residual stress is possible on a single crystal silicon substrate at high temperature, and these may result in micro-pinholes. Our results imply that the natural oxide layer removal process is of importance to ensure the successful completion of the silicide process with CoNi alloy films.