• Journal of Electrochemical Science and Technology
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• 제8권1호
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• pp.69-76
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• 2017

Crystallization of one-dimensional porous tin oxide during the anodic oxidation of tin at ambient temperatures is reported. Remarkable crystallinity is achieved when a substrate with a high elastic modulus (e.g., silicon) is used and the tin coating on it is very thin. It is suggested that the compressive stress applied to the anodic tin oxide during the anodization process is the key factor affecting the degree of crystallinity. The measured value of the stress generated during anodization matches well with the range of the most favorable theoretical pressure (stress) for crystallization.

• Journal of Sensor Science and Technology
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• 제7권1호
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• pp.73-82
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• 1998

In silicon surface micro-machining, the newly developed GPE(gas-phase etching) process was verified as a very effective method for the release of highly compliant micro-structures. The developed GPE system with anhydrous HF gas and $CH_{3}OH$ vapor was characterized and the selective etching properties of sacrificial layers to release silicon micro-structures were discussed. P-doped polysilicon and SOI(silicon on insulator) substrate were used as a structural layer and TEOS(tetraethyorthdsilicate) oxide, thermal oxide and LTO(low temperature oxide) as a sacrificial layer. Compared with conventional wet-release, we successfully fabricated micro-structures with virtually no process-induced striction and residual product.

• Korean Journal of Materials Research
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• 제3권1호
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• pp.7-11
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• 1993

Abstract Oxidation kinetics of silicon oxide films formed by rapid thermal oxidizing Si substrate in $N_2$O ambient studied. The data on $N_2$0 oxidation shows that the interfacial nitrogen-rich layers results in oxide growth in the parabolic regime by impeding oxidant diffusion to the Si$O_2$-Si interface even for ultrathin oxides. The activation energy of parablic rate constant, B, is about 1.5 eV, and the energy increses with oxide thickness.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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• pp.109-109
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• 2000

Recently, carbon nanotube has been investigating for field emission display ( (FED) applications due to its high electron emission at relatively low electric field. However, the growing of carbon nanotube generally requires relatively high temperature processing such as arc-discharge (5,000 ~ $20,000^{\circ}C$) and laser evaporation (4,000 ~ $5,000^{\circ}C$) methods. In this presentation, low temperature growing of carbon nanotube by plasma enhanced chemical vapor deposition (PECVD) using nickel catalyst which is compatible to conventional FED processing temperature will be described. Carbon n notubes with average length of 100 run and diameter of 2 ~ $3\mu$ill were successfully grown on silicon substrate with native oxide layer at $550^{\circ}C$using nickel catalyst. The morphology and microstructure of carbon nanotube was highly depended on the processing temperature and nickel layer thickness. No significant carbon nanotube growing was observed with samples deposited on silicon substrates without native oxide layer. This is believed due to the formation of nickel-silicide and this deteriorated the catalytic role of nickel. The formation of nickel-silicide was confirmed by x-ray analysis. The role of native oxide layer and processing parameter dependence on microstructure of low temperature grown carbon nanotube, characterized by SEM, TEM XRD and R없nan spectroscopy, will be presented.

• Proceedings of the KIEE Conference
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• 대한전기학회 1994년도 하계학술대회 논문집 C
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• pp.1463-1465
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• 1994

The electrical characteristics of $Al/Ta_2O_5/Si$ metal-oxide-semiconductor (MOS) capacitors were studied. $Ta_2O_5$ films on p-type silicon had been prepared by ionized cluster beam epitaxy technique (ICBE). This $Ta_2O_5$ films have low leakage current, high breakdown strength and low flat band shift. In this research, a single crystalline cpitaxial film of $Ta_2O_5$ has been grown on p-Si wafer using an ICBE technique. The native oxide layer ($SiO_2$) on the silicon substrate was removed below $500^{\circ}C$ by use of an accelerated arsenic ion beam, instead of a high temperature deposition. $Ta_2O_5$ films formed by ICBE technique can be received considerable attention for applications to coupling capacitors, gate dielectrics in MOS devices, and memory storage capacitor insulator because of their high dielectric constants above 20 and low temperature process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제28권11호
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• pp.698-703
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• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제30A권1호
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• pp.44-50
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• 1993

In an attempt to improve the electrical characteristics of tantalum pentoxide dielectric film, silicon substrate was reacted with a nitrogen plasma to form a silicon nitride of 50.angs. and then tantalum pentoxide thin films were formed by reactive sputtering in the same chamber. Breakdown field and leakage current density were measured to be 2.9 MV/cm and 9${\times}10^{8}\;A/cm^{2}$ respectively in these films whose thickness was about 180.angs.. With annealing at rectangular waveguides with a slant grid are investigated here. In particular, 900.deg. C in oxygen ambient for 100 minutes, breakdown field and leakage current density were improved to be 4.8 MV/cm and 1.61.6${\times}10^{8}\;A/cm^{2}$ respectively. It turned out that the electrical characteristics could also be improved by oxygen plasma post-treatment and the conduction mechanism at high electric field proved to be Schottky emission in these double-layered films.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제47권1호
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• pp.1-5
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• 2010

In this paper, we directly compare the program efficiency of conventional channel hot electron (CHE) injection methods and a novel hot electron injection methods using substrate forward biases in our silicon-oxide-nitride-oxide-silicon (SONOS) cell. Compared with conventional CHE injection methods, the proposed injection method showed improved program efficiency including faster program operation at lower bias voltages as well as localized trapping features for multi-bit operation with a threshold voltage difference of 1 V at between the forward and reverse read. This program method is expected to be useful and widely applied for future nano-scale multi-bit SONOS memories.

• Proceedings of the Korean Vacuum Society Conference
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.178-178
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• 2010

With the scaling down of ULSI(Ultra Large Scale Integration) circuit of CMOS(Complementary Metal Oxide Semiconductor)based electronic devices, the electronic devices become more faster and smaller size that are promising field of semiconductor market. However, very narrow line width has some disadvantages. For example, because of narrow line width, deposition of conformal and thin barrier is difficult. Besides, proportion of barrier width is large, thus resistance is high. Conventional PVD(Physical Vapor Deposition) thin films are not able to gain a good quality and conformal layer. Hence, in order to get over these side effects, deposition of thin layer used of ALD(Atomic Layer Deposition) is important factor. Furthermore, it is essential that copper atomic diffusion into dielectric layer such as silicon oxide and hafnium oxide. If copper line is not surrounded by diffusion barrier, it cause the leakage current and devices degradation. There are some possible methods for improving the these secondary effects. In this study, TaNx, is used of Tertiarybutylimido tris (ethylamethlamino) tantalum (TBITEMAT), was deposited on the 24nm sized trench silicon oxide/silicon bi-layer substrate with good step coverage and high quality film using plasma enhanced atomic layer deposition (PEALD). And then copper was deposited on TaNx barrier using same deposition method. The thickness of TaNx was 4~5 nm. TaNx film was deposited the condition of under $300^{\circ}C$ and copper deposition temperature was under $120^{\circ}C$, and feeding time of TaNx and copper were 5 seconds and 5 seconds, relatively. Purge time of TaNx and copper films were 10 seconds and 6 seconds, relatively. XRD, TEM, AFM, I-V measurement(for testing leakage current and stability) were used to analyze this work. With this work, thin barrier layer(4~5nm) with deposited PEALD has good step coverage and good thermal stability. So the barrier properties of PEALD TaNx film are desirable for copper interconnection.

• Journal of the Korean Vacuum Society
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• 제6권4호
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• pp.326-336
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• 1997

From the concept that the ion implantation-induced defect is one of the major factors in determining source/drain junction characteristics, high quality ultra-shallow $p^+$-n junctions were formed through the control of ion implantation-induced defects in silicon substrate. In conventional process of the junction formation. $p^+$ source/drain junctions have been formed by $^{49}BF_2^+$ ion implantation followed by the deposition of TEOS(Tetra-Ethyl-Ortho-Silicate) and BPSG(Boro-Phospho-Silicate-Glass) films and subsequent furnace annealing for BPSG reflow. Instead of the conventional process, we proposed a series of new processes for shallow junction formation, which includes the additional low temperature RTA prior to furnace annealing, $^{49}BF_2^+/^{11}B^+$ mixed ion implantation, and the screen oxide removal after ion implantation and subsequent deposition of MTO (Medium Temperature CVD oxide) as an interlayer dielectric. These processes were suggested to enhance the removal of ion implantation-induced defects, resulting in forming high quality shallow junctions.