• Journal of information and communication convergence engineering
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• v.3 no.4
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• pp.179-183
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• 2005

A photodiode capable of obtaining a sufficient photo/ dark current ratio at both forward bias state and reverse bias state is proposed. The photodiode includes a glass substrate, an aluminum film formed as a lower electrode over the glass substrate, an alumina film formed as an insulator barrier over the aluminum film, a hydrogenated amorphous silicon film formed as a photo conduction layer over a portion of the alumina film, and a transparent conduction film formed as an upper electrode over the hydro-generated amorphous silicon film. A good quality alumina $(Al_2O_3)$ film is formed by oxidation of aluminum film using electrolyte solution of succinic acid. Alumina is used as a potential barrier between amorphous silicon and aluminum. It controls dark-current restriction. In case of photodiodes made by changing the formation condition of alumina, we can obtain a stable dark current $(\~10^{-12}A)$ in alumina thickness below $1000{\AA}$. At the reverse bias state of the negative voltage in ITO (Indium Tin Oxide), the photo current has substantially constant value of $5{\times}10^{-9}$ A at light scan of 100 1x. On the other hand, the photo/dark current ratios become higher at smaller thicknesses of the alumina film. Therefore, the alumina film is used as a thin insulator barrier, which is distinct from the conventional concept of forming the insulator barrier layer near the transparent conduction film. Also, the structure with the insulator thin barrier layer formed near the lower electrode, opposed to the ITO film, solves the interface problem of the ITO film because it provides an improved photo current/dark current ratio.

• Korean Journal of Metals and Materials
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• v.47 no.7
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• pp.423-432
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• 2009

In the galvanizing coating process, the effects of the silicon content on the coatability and wettability of molten zinc were investigated on Dual-Phase High Strength Steels (DP-HSS) with various Si contents using the galvanizing simulator and dynamic reactive wetting systems. DP-HSS showed good coatability and a well-developed inhibition layer in the range of Si content below 0.5 wt%. Good coatability was the results of the mixed oxide $Mn_{2}SiO_{4}$, being formed by the selective oxidation on the surface, with a low contact angle in molten zinc and a large fraction of oxide free surface that provided a sufficient site for the molten zinc to wet and react with the substrate. On the other hand, with more than 0.5 wt%, DP-HSS exhibited poor coatability and an irregularly developed inhibition layer. The poor coatability was due to the poor wettability that resulted from the development of network-type layers of amorphous ${SiO}_{2}$, leading to a high contact angle in molten zinc, on the surface.

• Journal of Sensor Science and Technology
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• v.11 no.3
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• pp.163-170
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• 2002

This paper proposes a $10\;{\mu}m$ thick oxide air-bridge structure which can be used as a substrate for RF circuits. The structure was fabricated by anodic reaction, complex oxidation and micromachining technology using TMAH etching. High quality films were obtained by combining low temperature thermal oxidation ($500^{\circ}C$, 1 hr at $H_2O/O_2$) and rapid thermal oxidation (RTO) process ($1050^{\circ}C$, 2 min). This structure is mechanically stable because of thick oxide layer up to $10\;{\mu}m$ and is expected to solve the problem of high dielectric loss of silicon substrate in RF region. The properties of the transmission line formed on the oxidized porous silicon (OPS) air-bridge were investigated and compared with those of the transmission line formed on the OPS layers. The insertion loss of coplanar waveguide (CPW) on OPS air-bridge was (about 2dB) lower than that of CPW on OPS layers. Also, the return loss of CPW on OPS air-bridge was less than about -20 dB at measured frequency region for 2.2 mm. Therefore, this technology is very promising for extending the use of CMOS circuitry to higher RF frequencies.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.04b
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• pp.38-41
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• 2002

The variation of photoluminescence(PL) properties of Si thin films was investigated by changing deposition temperatures, Si-rich silicon oxide films on p-type (100) Si substrate have been fabricated by pulsed laser deposition(PLD) technique using a Nd:YAG laser. During deposition, the substrates were kept at the temperature range of room temperature(RT) to $400^{\circ}C$. After deposition, samples were annealed at $800^{\circ}C$ in nitrogen ambient, Strong Blue PL has been observed on RT-deposited Si nanocrystallites. When the deposition temperature was increased over $100^{\circ}C$, PL intensities abruptly decreased. The experimental results show the growing mechanism of Si nanocrystallites by PLD.

• Journal of Sensor Science and Technology
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• v.17 no.1
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• pp.35-40
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• 2008

Low power bridge type micro gas sensors were fabricated by micro machining technology with TMAH (Tetra Methyl Ammonium Hydroxide) solution. The sensing devices with different heater materials such as metal and poly-silicon were obtained using CMOS (Complementary Metal Oxide Semiconductor) compatible process. The tellurium films as a sensing layer were deposited on the micro machined substrate using shadow silicon mask. The low power micro gas sensors showed high sensitivity to NO with high speed. The pure tellurium film used micro gas sensor showed good sensitivity than transition metal (Pt, Ti) used tellurium film.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.300-300
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• 2011

Si oxidation is a key process in developing silicon devices, such as highly integrated metal-oxide-semiconductor (MOS) transistors and antireflection-coating (ARC) on solar cell substrate. Many experimental and theoritical studies have been carried out for elucidating oxidation processes and adsorption structure using ab initio total energy and electronic structure calcultaions. However, the initial oxidation processes at step edge on vicinal Si surface have not been studied using the ReaxFF reactive force field. In this work, strucutural change, charge distribution of oxidized Si throughout the depth from Si surface were observed during oxidation processes on vicinal Si(001) surface inclined by $10.5^{\circ}$ of miscut angle toward [100]. Adsorption energys of step edge and flat terrace were calculated to compare the oxidation reaction at step edge and flat terrace on Si surface.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.109-110
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• 2013

Medium carbon steel was aluminized by hot dipping into molten Al or Al-1%Si baths. After hot-dipping in these baths, a thin Al-rich topcoat and a thick alloy layer rich in $Al_5Fe_2$ formed on the surface. A small a mount of FeAl and $Al_3Fe$ was incorporated in the alloy layer. Silicon from the Al-1%Si bath was uniformly distributed throughout the entire coating. The hot dipping increased the microhardness of the steel by about 8 times. Heating at $700-1000^{\circ}C$ however decreased the microhardness through interdiffusion between the coating and the substrate. The oxidation at $700-1000^{\circ}C$ in air formed a thin protective ${\alpha}-Al_2O_3$ layer, which provided good oxidation resistance. Silicon was oxidized to amorphous silica, exhibiting a glassy oxide surface.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.595-596
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• 2006

A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of $20{\mu}m$ is fabricated and the electrical and mechanical characteristics of via are under testing.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.7
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• pp.760-765
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• 1992

The material properties and the TFT characteristics fabricated on SiOS12T substrate by LPCVD using SiHS14T gas were investigated. The deposition rate showed Arrhenius behavior with an activation energy of 31Kcal/mol. And the transition temperature form amorphous to crystalline deposition was observed at 570$^{\circ}C$-580$^{\circ}C$. The strong(220) texture was observed as the deposition temperature increases. XRD analysis showed that the film texture of the as-deposited polycrystalline silicon does not change after annealing at 850$^{\circ}C$. The fabricated TFT's based on the as-deposited amorphous film showed superior electrical characteristics to those of the as-deposited polycrystalline films. It is considered that the different electrical characteristics result from the difference of flat band voltage(VS1FBT) due to the interface trap density between the gate oxide and the active channel.