• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.10
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• pp.1494-1498
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• 2017

In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage ($V_{dd}$) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high $I_{on}/I_{off}$ ratios are major factors that enable the excellent operation of the logic gate.

• Journal of Electrical Engineering and Technology
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• v.8 no.5
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• pp.1163-1168
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• 2013

In this paper, Adaptive Neuro-Fuzzy Inference System (ANFIS) is applied for modeling and simulation of DC characteristic of cylindrical Silicon Nanowire Transistor (SNWT). Device Geometry parameters, terminal voltages, temperature and output current were selected as the main factors of modeling. The results obtained are compared with numerical method and a good match has been observed between them, which represent accuracy of model. Finally, we imported the ANFIS model as a voltage controlled current source in a circuit simulator like HSPICE and simulated a SNWT inverter and common-source amplifier by this model.

• Transactions on Electrical and Electronic Materials
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• v.13 no.2
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• pp.73-77
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• 2012

Operation of liquid crystal displays (LCDs) can be improved by monolithic integration of the pixel transistors with light emitting diodes (LEDs) on a single substrate. Conventional LCDs make use of filters to control the backlighting which reduces the overall efficiency. These LCDs also utilize LEDs in series which impose failure and they require high voltage for operation with a power factor correction. The screen of small hand-held devices can operate from moderate brightness. Therefore, III-V nanowires that are grown along with transistors over Silicon substrates can be utilized. Control of nanowire LEDs with nanowire transistors will significantly lower the cost, increase the efficiency, improve the manufacturing yield and simplify the structure of the small displays that are used in portable devices. The steps to grow nanowires on Silicon substrates are described. The vertical n-type and p-type nanowire transistors with surrounding gate structures are characterized. While biased at 0.5 V, nanowire transistors with minimum radius or channel width have an OFF current which is less than 1pA, an ON current more than 1 ${\mu}A$, a total delay less than 10 ps and a transconductance gain of more than 10 ${\mu}A/V$. The low power and fast switching characteristics of the nanowire transistor make them an ideal choice for the realization of future displays of portable devices with long battery lifetime.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.434-438
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• 2014

CMOS의 최종형태로써 Gate-All-Around(GAA) Silicon Nanowire(NW)가 각광받고 있다. 이 논문에서 NW FET(Field Effect Transistor)의 채널 길이와 NW의 폭과 같은 size에 따른 특성변화를 실제 실험 data와 NW FET 특성분석 simulation을 이용해서 비교해보았다. MOSFET(Metal Oxide Semiconductor Field Effect Transistor)의 소형화에 따른 쇼트 채널 효과(short channel effect)에 의한 threshold voltage($V_{th}$), Drain Induced Barrier Lowering(DIBL), subthreshold swing(SS) 또한 비교하였다. 이에 더하여, 기존의 상용툴로 NW를 해석한 시뮬레이션 결과와도 비교해봄으로써 NW의 size scaling에 대한 EDISON NW 해석 simulation의 정확도를 파악해보았다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.451-456
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• 2014

A compact model of a depletion-mode silicon-nanowire (Si-NW) pH sensor is proposed. This drain current model is obtained from the Pao-Sah integral and the continuous charge-based model, which is derived by applying the parabolic potential approximation to the Poisson's equation in the cylindrical coordinate system. The threshold-voltage shift in the drain-current model is obtained by solving the nonlinear Poisson-Boltzmann equation for the electrolyte. The simulation results obtained from the proposed drain-current model for the Si-NW field-effect transistor (SiNWFET) agree well with those of the three-dimensional (3D) device simulation, and those from the Si-NW pH sensor model also agree with the experimental data.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.413-413
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• 2009

Silicon nanowires (Si NWs)-based top-gate field-effect transistors (FETs) are constructed by using Si NWs transferred onto flexible plastic substrates. Si NWs are obtained from the silicon wafers using photolithography and anisotropic etching process, and transferred onto flexible plastic substrates. To evaluate the electrical performance of the silicon nanowires, we examined the output and transfer characteristics of a top-gate field-effect transistor with a channel composed of a silicon nanowire selected from the nanowires on the plastic substrate. From these FETs, a field-effect mobility and transconductance are evaluated to be $47\;cm^2/Vs$ and 272 nS, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.486-486
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• 2013

Silicon nanowire devices fabricated by bottom-up methods are attracted due to their electrical, mechanical, and optical properties. Especially, to functionalize the surface of silicon nanowires by molecules has received interests. The changes in the characteristics of the molecules is delivered directly to the surface of the silicon nanowires so that the silicon nanowire can be utilized as an efficient read-out device by using the electronic state change of molecules. The surface treatment of the silicon nanowire with light-sensitive molecules can change its optical characteristics greatly. In this paper, we present the optical response of a SiNW field-effect-transistor (FET) conjugated with porphyrin molecules. We fabricated a SiNW FET and performed porphyrin conjugation on its surface. The characteristic and the optical response of the device shows a large difference after conjugation while there is not much change of the surface in the SEM observation. It attributed to the existence of few layer porphyrin molecules on the SiNW surface and efficient variation of the surface potential of the SiNW due to light irradiation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2892-2898
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• 2015

We propose a new Double-Independent-Gate Ambipolar Silicon-Nanowire Field Effect Transistor(DIG Ambi-SiNWFET). The proposed transistor has two types of gate such as polarity gate and control gate. The polarity gate determines the operation that the gate bias controls NMOSFET or PMOSFET. The voltage of control gate controls the current characteristic of the transistor. We investigated systematically work functions of the two gates and source/drain to operate ambipolar current-voltage characteristics using 2D device simulator. When the work functions of polarity gate, control gate and source/drain are 4.75eV, 4.5eV, and 4.8eV, respectively, it showed the obvious ambipolar characteristics.

• Journal of the Korean Society for Precision Engineering
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• v.30 no.1
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• pp.128-133
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• 2013

Si Nanowire (Si-NW) arrays were fabricated by top-down method. A relatively simple method is suggested to fabricate suspended silicon nanowire arrays. This method allows for the production of suspended silicon nanowire arrays using anisotropic wet etching and conventional MEMS method of SOI (Silicon-On-Insulator) wafer. The dimensions of the fabricated nanowire arrays with the proposed method were evaluated and their effects on the Field Effect Transistor (FET) characteristics were discussed. Current-voltage (I-V) characteristics of the device with nanowire arrays were measured using a probe station and a semiconductor analyzer. The electrical properties of the device were characterized through leakage current, dielectric property, and threshold voltage. The results implied that the electrical characteristics of the fabricated device show the potential of being ion-selective field effect transistors (ISFETs) sensors.