• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.118-119
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• 2009

This paper presents the feature profile evolution silicon deep trench etching, which is very crucial for the commercial wafer process application. The silicon deep trenches were etched with the SF6 gas & Hbr gas based process recipe. The optimized silicon deep trench process resulted in vertical profiles (87o~90o) with loading effect of < 1%. The process recipes were developed for the silicon deep trench etching applications. This scheme provides vertically profiles without notching of top corner was observed. In this study, the production of SF6 gas based silicon deep trench etch process much more strongly than expected on the basis of Hbr gas trench process that have been investigated by scanning electron microscope (SEM). Based on the test results, it is concluded that the silicon deep trench etching shows the sufficient profile for practical MOS FET silicon deep trench technology process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.19-20
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• 2006

Two methods that can reduce reflectance in solar cells are surface texturing and anti-reflection coating. Wet chemical etching is a typical method that surface texturing of multi-crystalline silicon. Wet chemical etching methods are the acid texturization of saw damage on the surface of multi-crystalline silicon or double-step chemical etching after KOH saw damage removal too. These methods of surface texturing are realized by chemical etching in acid solutions HF-$HNO_3$-$H_2O$. In this solutions we can reduce reflectance spectra by simple process etching of multi-crystalline silicon surface. We have obtained reflectance of 27.19% m 400~1100nm from acidic chemical etching after KOH saw damage removal. This result is about 7% less than just saw damage removal substrate. The surface morphology observed by microscope and scanning electron microscopy (SEM).

• 한국진공학회지
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• 제6권3호
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• pp.242-248
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• 1997

기존의 다공질 실리콘 제작 방법인 chemical etching 방법을 병행하면서 새로운 제 작 방법으로서 dry etching 기술을 적용하여 다공질 실리콘을 제작하였다. 또한, 비교를 위 해 E-beam lithography 기술로 실리콘 구조물을 제작하였는데 이 경우 기술상 문제로 약 0.3$\mu\textrm{m}$의 직경을 가진 구조물이 최소의 크기였다. 따라서 새로운 방법으로 4인치 wafer위에 mask 역할을 해주는 다이아몬드 분말을 spin coater로 입힌 후 Reactive Ion Etching(RIE) 방법으로 미세구조의 다공질 실리콘을 제작하였다. 다양한 조건으로 제작된 sample들의 morphology를 SEM과 AFM 등을 이용하여 분석하였고 이 morphology에 대응하는 PL스펙 트럼을 측정하였다. 그 결과, 다이아몬드 분말을 이용한 dry etching방법으로 제작된 다공질 실리콘의 PL peak의 위치가 chemical etching 방법의 다공질 실리콘의 PL peak 위치인 760nm에 비해 높은 에너지인 590nm로 나타났다.

• 전기학회논문지
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• 제56권12호
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• pp.2221-2225
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• 2007

Hollow-type microneedle array can be used for painless, continuous and stable drug delivery through a human skin. The needles must be sharp and have sufficient length in order to penetrate the epidermis. An array of hollow-type silicon microneedles was fabricated by using deep reactive ion etching and HNA wet etching with two oxide masks. Isotropic etching was used to create tapered tips of the needles, and anisotropic etching of Bosch process was used to make the extended length and holes of microneedles. The microneedles were formed by three steps of isotropic, anisotropic, and isotropic etching in order. The holes were made by one anisotropic etching step. The fabricated microneedles have $170{\mu}m$ width, $40{\mu}m$ hole diameter and $230{\mu}m$ length.

• 한국전기전자재료학회논문지
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• 제18권12호
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• pp.1106-1110
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• 2005

We fabricated (110) silicon hard master by using anisotropic wet etching for embossing. The etching chemical for the silicon wafer was a TMAH $25\%$ solution. The anisotropic wet etching produces a smooth sidewall surface and the surface roughness of the fabricated master is about 3 nm. After spin coating an organic-inorganic sol-gel hybrid material on a silicon substrate, we employed hot embossing technique operated at a low pressure and temperature to form patterns on the silicon substrate by using the fabricated master. We successfully fabricated the multi-mode planar optical waveguides showing low propagation loss of 0.4 dB/cm. The surface roughness of embossed patterns was uniform for more than 10 times of the embossing processes with a single hydrophobic surface treatment of the silicon hard master.

• Transactions on Electrical and Electronic Materials
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• 제16권6호
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• pp.312-316
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• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.237-240
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• 2001

In this paper, we have presented processing technique about wet etching for silicon membrane construction formation. In order to make selective etching of backside silicon wafer, we used Si$_3$N$_4$ layer by PECVD(Plasma Enhanced Chemical Vapor Deposition). We have measured the surface thickness in backside silicon wafer after anisortropic wet etching with KOH:distilled water solutions. Through this experiment, we acquired the etching rate for 1.29${\mu}{\textrm}{m}$/min. The average rough of Si-membrane frontside and backside was 0.26${\mu}{\textrm}{m}$, 0.90${\mu}{\textrm}{m}$, respectively.

• 통합자연과학논문집
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• 제6권3호
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• pp.170-175
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• 2013

Silicon nanowires were detached and obtained from silicon nanowire arrays on silicon substrate using a ultrasono-method. Silicon nanowire arrays on silicon substrate were prepared with an electroless metal assisted etching of p-type silicon. The etching solution was an aqueous HF solution containing silver nitrate. SEM observation shows that well-aligned nanowire arrays perpendicular to the surface of the silicon substrate were produced. After sonication of silicon nanowire array, an individual silicon nanowire was confirmed by FESEM. Optical characteristics of SiNWs were measured by FT-IR spectroscopy. The surface of SiNWs are terminated with hydrogen.

• 마이크로전자및패키징학회지
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• 제18권1호
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• pp.23-27
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• 2011

전기화학적 에칭을 이용한 다공성 실리콘 이중층 형성은 초박형 태양전지 제작에서 PS layer transfer 기술을 적용하기 위한 선행 공정이다. 다공성 실리콘 층의 다공도는 전류밀도와 에칭용액 내 불산의 농도를 조절하여 제어할 수 있다. 전기화학적 에칭을 이용한 다공성 실리콘 형성을 위하여 비저항 $0.01-0.02\;{\Omega}{\cdot}cm$의 p-type (100)의 실리콘 웨이퍼를 사용하였으며, 에칭용액의 조성은 HF (40%) : $C_2H_5OH$(99 %) : $H_2O$ = 1 : 1 : 2 (volume)으로 고정하였다. PS layer transfer 기술에 사용되는 다공성 실리콘 이중층을 형성하기 위해서 에칭 도중 전류밀도를 낮은 전류밀도 조건에서 높은 전류밀도 조건으로 변환하여 low porosity layer 하부에 high porosity layer를 형성할 수 있다.

• 한국전기전자재료학회논문지
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• 제22권7호
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• pp.616-621
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• 2009

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating(ARC) and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si ARC layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layers were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The structure of porous Si layers was investigated with SEM. The formation of a nanoporous Si layer about 100nm thick on the textured silicon wafer result in a reflectance lower than 5% in the wavelength region from 500 to 900nm. Such a surface modification allows improving the Si solar cell characteristics. An efficiency of 13.4% is achieved on a monocrystalline silicon solar cell using the electrochemical technique.