• Journal of the Korean Crystal Growth and Crystal Technology
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• v.25 no.1
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• pp.13-19
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• 2015

Among the various possible factors affecting the Minority Carrier Life Time (MCLT) of the mc-Si crystal, dislocations formed during the cooling period after solidification were found to be a major element. It was confirmed that other defects such as grain boundary or twin boundary were not determinative defects affecting the MCLT because most of these defects seemed to be formed during the solidification period. With a measurement of total thickness variation (TTV) and bow of the silicon wafers, it was found that residual stress remaining in the mc-Si crystal might be another major factor affecting the MCLT. Thus, it is expected that better quality of mc-Si can be grown when the cooling process right after solidification is carried out as slow as possible.

• Transactions on Electrical and Electronic Materials
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• v.7 no.6
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• pp.301-304
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• 2006

We studied the nematic liquid crystal (NLC) aligning capabilities using the new alignment material of the SiC (Silicon Carbide) thin film. The SiC thin film exhibits good chemical and thermal stability. The good thermal and chemical stability make SiC an attractive candidate for electronic applications. A vertical alignment of nematic liquid crystal by atomic beam exposure on the SiC thin film surface was achieved. The about $87^{\circ}$ of stable pretilt angle was achieved at the range from $30^{\circ}\;to\;45^{\circ}$ of incident angle. Consequently, the vertical alignment effect of liquid crystal electro-optical characteristic by the atomic beam alignment method on the SiC thin film layer can be achieved.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 2000.06a
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• pp.87-125
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• 2000

A new paradigm of crystal growth was suggested in a charged cluster model, where charged clusters of nanometer size are suspended in the gas phase in most thin film processes and are a major flux for thin film growth. The existence of these hypothetical clusters was experimentally confirmed in the diamond and silicon CVD processes as well as in gold and tungsten evaporation. These results imply new insights as to the low pressure diamond synthesis without hydrogen, epitaxial growth, selective deposition and fabrication of quantum dots, nanometer-sized powders and nanowires or nanotubes. Based on this concept, we produced such quantum dot structures of carbon, silicon, gold and tungsten. Charged clusters land preferably on conducting substrates over on insulating substrates, resulting in selective deposition. if the behavior of selective deposition is properly controlled, charged clusters can make highly anisotropic growth, leading to nanowires or nanotubes.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.6
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• pp.254-261
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• 2010

Polycrystalline silicon (pc-Si) films are fabricated and characterized for application to pc-Si thin film solar cells as a seed layer. The amorphous silicon films are crystallized by the aluminum-induced layer exchange (ALILE) process with a structure of glass/Al/$Al_2O_3$/a-Si using various thicknesses of $Al_2O_3$ layers. In order to investigate the effects of the oxide layer on the crystallization of the amorphous silicon films, such as the crystalline film detects and the crystal grain size, the $Al_2O_3$ layer thickness arc varied from native oxide to 50 nm. As the results, the defects of the poly crystalline films are increased with the increase of $Al_2O_3$ layer thickness, whereas the grain size and crystallinity are decreased. In this experiments, obtained the average pc-Si sub-grain size was about $10\;{\mu}m$ at relatively thin $Al_2O_3$ layer thickness (${\leq}$ 16 nm). The preferential orientation of pc-Si sub-grain was <111>.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Korean Journal of Materials Research
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• v.17 no.4
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• pp.207-214
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• 2007

We fabricated thermally-evaporated 10 -Ni/(poly)Si and 10 -Ni/1 -Ir/(poly)Si structures to investigate the microstructure of nickel monosilicide at the elevated temperatures required for annealing. Silicides underwent rapid at the temperatures of 300-1200 for 40 seconds. Silicides suitable for the salicide process formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester was used to investigate the sheet resistances. A transmission electron microscope(TEM) and an Auger depth profile scope were employed for the determination of vertical section structure and thickness. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates shoed low resistance up to 1000 and 800, respectively, while the conventional nickle monosilicide showed low resistance below 700. Through TEM analysis, we confirmed that a uniform, 20 -thick silicide layer formed on the single-crystal silicon substrate for the Ir-inserted case while a non-uniform, agglomerated layer was observed for the conventional nickel silicide. On the polycrystalline silicon substrate, we confirmed that the conventional nickel silicide showed a unique silicon-silicide mixing at the high silicidation temperature of 1000. Auger depth profile analysis also supports the presence of thismixed microstructure. Our result implies that our newly proposed iridium-added NiSi process may widen the thermal process window for the salicide process and be suitable for nano-thick silicides.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.22 no.2
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• pp.65-72
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• 2012

Aluminum induced crystallization of amorphous silicon was attempted by the aluminum substrate. To avoid the layer exchange between silicon and aluminum layer, Ni layer was deposited between these two layers by sputtering. To obtain the bigger grain of the crystalline silicon, wet blasted silica layer was employed as windows between the nickel and a-Si layer. Ni obtained after the annealing treatment at $520^{\circ}C$ was found to be a promising material for the diffusion barrier between silicon and aluminum. One way to obtain bigger grain of crystalline silicon layer applicable to solar cell of higher performance was envisioned in this investigation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.308-317
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• 2007

We fabricated thermally-evaporated 10 nm-Ni/(poly)Si and 10 nm-$Ni_{0.5}Co_{0.5}$/(Poly)Si structures to investigate the microstructure of nickel silicides at the elevated temperatures required lot annealing. Silicides underwent rapid annealing at the temperatures of $600{\sim}1100^{\circ}C$ for 40 seconds. Silicides suitable for the salicide process formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester was used to investigate the sheet resistances. A transmission electron microscope and an Auger depth profilescope were employed for the determination of vortical microstructure and thickness. Nickel silicides with cobalt on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1100^{\circ}C$ and $900^{\circ}C$, respectively, while the conventional nickle monosilicide showed low resistance below $700^{\circ}C$. Through TEM analysis, we confirmed that a uniform, $10{\sim}15 nm$-thick silicide layer formed on the single-crystal silicon substrate for the Co-alloyed case while a non-uniform, agglomerated layer was observed for the conventional nickel silicide. On the polycrystalline silicon substrate, we confirmed that the conventional nickel silicide showed a unique silicon-silicide mixing at the high silicidation temperature of $1000^{\circ}C$. Auger depth profile analysis also supports the presence of this mixed microstructure. Our result implies that our newly proposed NiCo-alloy composite silicide process may widen the thermal process window for the salicide process and be suitable for nano-thick silicides.

• Journal of Industrial Technology
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• v.2
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• pp.13-19
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• 1982

Polycrystalline silicon layers have been deposited by a chemical vapor deposition technique using $SiCl_4$, $H_2$ gas mixture on single crystal silicon substrates. In this work, the effects of depostion temperature and total flow rate on the deposition rate of polycrystalline silicon are investigated. From the experimental results it was found that the formation reaction of polycrystalline silicon was limited by surface reaction and mass transfer controlled as the deposition temperature was increased. The morphology of polycrystalline silicon layer changed from a fine structure to a coarse one as the deposition temperature was increased.

• Korean Journal of Materials Research
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• v.18 no.10
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• pp.521-528
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• 2008

We present the structural, optical, and electrical properties of amorphous silicon suboxide (a-$SiO_x$) films grown on indium tin oxide glass substrates with a radio frequency magnetron technique from a polycrystalline silicon oxide target using ambient Ar. For different substrate-target distances (d = 8 cm and 10 cm), the deposition temperature effects were systematically studied. For d = 8cm, oxygen content in a-$SiO_x$ decreased with dissociation of oxygen onto the silicon oxide matrix; temperature increased due to enlargement of kinetic energy. For d = 10 cm, however, the oxygen content had a minimum between $150^{\circ}\;and\;200^{\circ}$. Using simple optical measurements, we can predict a preferred orientation of liquid crystal molecules on a-$SiO_x$ thin film. At higher oxygen content (x > 1.6), liquid crystal molecules on an inorganic liquid crystal alignment layer of a-$SiO_x$ showed homogeneous alignment; however, in the lower case (x < 1.6), liquid crystals showed homeotropic alignment.