• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.470-480
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• 2016

The reversal of a silicon chip to find out its security structure is common and possible at the present time. Thanks to reversing, it is possible to use a probing attack to obtain useful information such as personal information or a cryptographic key. For this reason, security-related blocks such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and RSA (Rivest Shamir Adleman) engines should be located in the lower layer of the chip to guard against a probing attack; in this regard, the addition of a silicon-surface-protection layer onto the chip surface is a crucial protective measure. But, for manufacturers, the implementation of an additional silicon layer is burdensome, because the addition of just one layer to a chip significantly increases the overall production cost; furthermore, the chip size is increased due to the bulk of the secure logic part and routing area of the silicon protection layer. To resolve this issue, this paper proposes a practical silicon-surface-protection method using a metal layer that increases the security level of the chip while minimizing its size and cost. The proposed method uses a shift register for the alternation and variation of the metal-layer data, and the inter-connection area is removed to minimize the size and cost of the chip in a more extensive manner than related methods.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.29-36
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• 2004

A flexible packaging scheme, which includes chip packaging, has been developed using a thinned silicon chip. Mechanical characteristics of thinned silicon chips are examined by bending tests and finite element analysis. Thinned silicon chips (t<30 $\mu\textrm{m}$) are fabricated by chemical etching process to avoid possible surface damages on them. And the chips are stacked directly on $Kapton^{Kapton}$film by thermal compressive bonding. The low height difference between the thinned silicon chip and $Kapton^{Kapton}$film allows electroplating for electrical interconnection method. Because the 'Chip' is embedded in the flexible substrate, higher packaging density and wearability can be achieved by maximized usable packaging area.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.3
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• pp.14-19
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• 2008

In the semiconductor IC(Integrated Circuit) package, the top surface of silicon chip is directly attached to the area of the leadframe with a double-sided adhesive layer, in which the base layer have the upper adhesive layer and the lower adhesive layer. The IC package structure has been known to encounter a thermo-mechanical failure mode such as delamination. This failure mode is due to the residual stress on the adhesive surface of silicon chip and leadframe in the curing-cooling process. The induced thermal stress in the curing process has an influence on the cooling residual stress on the silicon chip and leadframe. In this paper, for the minimization of the chip surface damage, the adhesive topologies on the silicon chip are studied through the finite element analysis(FEA).

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.481-485
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• 1987

The fabrication of a micro mass flow sensor on a silicon chip by means of micro-machining technology is described on this paper. The operation of micro mass flow sensor is based on the heat transfer from a heated chip to a fluid. The temperature differences on the chip is a measure for the flow velocity in a plane parallel with the chip surface. An anisotropic etching technigue was used for the formation of the V-type groove in this fabrication. The micro mass flow sensor is made up of two main parts ; A thin glass plate embodying the connecting parts and mass flow sensor parts in silicon chip. This sensor have a very small size and a neglible dead space. Micro mass flow sensor can fabricate on silicon chip by micro machining technology too.

• Journal of Surface Science and Engineering
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• v.28 no.3
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• pp.174-181
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• 1995

Multilayered silicon cantilever beams as interconnection systems for bare chip burn-in socket applications have been designed, fabricated and characterized. Fabrication processes of the beam are employing standard semiconductor processes such as thin film processes and epitaxial layer growth and silicon wet etching techniques. We investigated silicon etch rate in 1-3-10 etchant as functions of doping concentration, surface mechanical stress and crystal defects. The experimental results indicate that silicon etch rate in 1-3-10 etchant is strong functions of doping concentration and crystal defect density rather than surface mechanical stress. We suggested the new fabrication processes of multilayered silicon cantilever beams.

• Transactions on Electrical and Electronic Materials
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• v.16 no.6
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• pp.312-316
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• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.1
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• pp.41-47
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• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.

• ETRI Journal
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• v.33 no.1
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• pp.13-17
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• 2011

A highly miniaturized on-chip $180^{\circ}$ hybrid employing periodic ground strip structure (PGSS) was realized on a silicon radio frequency integrated circuit. The PGSS was placed at the interface between $SiO_2$ film and silicon substrate, and it was electrically connected to top-side ground planes through the contacts. Owing to the short wavelength characteristic of the transmission line employing the PGSS, the on-chip $180^{\circ}$ hybrid was highly miniaturized. Concretely, the on-chip $180^{\circ}$ hybrid exhibited good radio frequency performances from 37 GHz to 55 GHz, and it was 0.325 $mm^2$, which is 19.3% of a conventional $180^{\circ}$ hybrid. The miniaturization technique proposed in this work can be also used in other fields including compound semiconducting devices, such as high electron mobility transistors, diamond field effect transistors, and light emitting diodes.

• Journal of Integrative Natural Science
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• v.3 no.4
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• pp.237-240
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• 2010

Recently, number of studies for porous silicon have been investigated by many researchers. Multistructured porous silicon (PSi), distributed Bragg reflector (DBR) PSi, has been a topic of interest, because of its unique optical properties. DBR PSi were prepared by an electrochemical etch of $P^{{+}{+}}$-type silicon wafer of resistivity between 0.1 $m{\Omega}cm$ with square wave current density, resulting two different refractive indices. In this work, We have fabricated a simple and portable organic vapor-sensing device based on DBR porous silicon and investigated the optical characteristics of DBR porous silicon. DBR porous silicon have been characterized by FT-IR, Ocean optics 2000 spectrometer. The device used DBR PSi chip has been demonstrated as an excellent gas sensor, showing a great senstivity to a toxic vapor (TEP, DMMP, DEEP) at room temperature.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.389-393
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• 2003

This paper presents circuit modeling and characterization of silicon-based on-chip integrated inductors in Giga Hertz range for wireless communication products. We compare several different designs of on-chip inductors for self-resonant frequency and quality factor. The measurement data could be used as a design guide for manufacturing practical spiral inductors for wireless applications. We provide the equivalent inductor circuit parameters from the actual measurement data.