• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 1997.04a
• /
• pp.921-926
• /
• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2003.06a
• /
• pp.223-227
• /
• 2003

A new flexible electronic packaging technology and its medical applications are presented. Conventional silicon chips and electronic modules can be considered as "mechanically rigid box." which does not bend due to external forces. This mechanically rigid characteristic prohibits its applications to wearable systems or bio-implantable devices. Using current MEMS (Microelectromechanical Systems) technology. a surface micromachined flexible polysilicon sensor array and flexible electrode array fer neural interface were fabricated. A chemical thinning technique has been developed to realize flexible silicon chip. To combine these techniques will result in a realization of truly flexible sensing modules. which are suitable for many medical applications.

• Journal of the Korean institute of surface engineering
• /
• v.27 no.2
• /
• pp.83-90
• /
• 1994

We have investigated the mechanism for the abnormal oxide growth occuring during oxidation of the crystalline tungsten silicide. TEM and XPS analysis reveal the abnormaly grown oxide layer consisting of crystalline $Wo_3$ and amorphous $SiO_2$. The presence of crystalline $Wo_3$ provides a rapid diffusion of oxygen through the oxide layer. The abnormal oxide growth is mainly due to the poor quality of initial oxide layer growth on tungsten silicide. Two species such as tungsten and silicon from decomposition fo tungsten silicide as well as silicon supplied from the underlying polysilicon are the main contributors sto abnormal oxide forma-tion. Consequently, the abnormal oxidation results in the disintegration of tungsten silicide and thinning of polysilicon as well.

• New & Renewable Energy
• /
• v.4 no.2
• /
• pp.74-80
• /
• 2008

To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

• 한국신재생에너지학회:학술대회논문집
• /
• 2008.05a
• /
• pp.390-393
• /
• 2008

To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.2
• /
• pp.1-9
• /
• 2013

Recently flexible electronic devices have attracted a great deal of attention because of new application possibilities including flexible display, flexible memory, flexible solar cell and flexible sensor. In particular, development of flexible memory is essential to complete the flexible integrated systems such as flexible smart phone and wearable computer. Research of flexible memory has primarily focused on organic-based materials. However, organic flexible memory has still several disadvantages, including lower electrical performance and long-term reliability. Therefore, emerging research in flexible electronics seeks to develop flexible and stretchable technologies that offer the high performance of conventional wafer-based devices as well as superior flexibility. Development of flexible memory with inorganic silicon materials is based on the design principle that any material, in sufficiently thin form, is flexible and bendable since the bending strain is directly proportional to thickness. This article reviews progress in recent technologies for flexible memory and flexible electronics with inorganic silicon materials, including transfer printing technology, wavy or serpentine interconnection structure for reducing strain, and wafer thinning technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.12
• /
• pp.1075-1079
• /
• 2005

The Pseudo MOSFET measurements technique has been used for the electrical characterization of the nano SOI wafer. Silicon islands for the Pseudo MOSFET measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo MOSFET were not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device were dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100 nm SOI was obtained by thinning the silicon film of standard thick SOI wafer. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching Process dependency is greater in the thinner SOI wafer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.3-4
• /
• 2005

The Pseudo-MOSFET measurements technique has been used for the electrical characterization of the nano SOL Silicon islands for the Pseudo-MOS measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo-MOS was not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device was dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100nm SOI was obtained by thinning the silicon film of standard thick SOI. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo-MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching process dependency is greater in the thinner SOI and related to original SOI wafer quality.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.196-203
• /
• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.08a
• /
• pp.130-132
• /
• 2003

ALD(Atomic Layer Deposition) 법으로 박막 알루미나를 형성한 후 웨이퍼 접합과 박막화 공정으로 알루미나를 매몰절연막으로 하는 SOI 구조를 제조하고 그 특성을 조사하였다. 알루미나 박막의 유전 특성과 실리콘과의 계면 특성은 C-V 측정으로, 단면 분석은 SEM(Scanning Electron Microscope) 촬영으로 조사하였다. 알루미나와 실리콘을 접합하기 위하여 1100C에서 열처리를 행한 후 알루미나와 실리콘의 계면 상태 밀도는 $2.5{\times}10^{11}/cm^2-eV$였다. 그리고 SEM의 단연 분석과 AES(Auger Electron Spectroscope)의 깊이 방향 분석을 통해서 매몰 알루미나층의 존재를 확인하였다. 알루미나는 실리콘 산화막보다 높은 열전도성을 가지므로 이를 매몰절연막으로 하여 SOI 구조를 제조하면 기존의 실리콘산화막을 매몰절연막으로 하는 SOI를 기판으로 하여 제조되는 소자보다 selg heating 효과가 감소된 우수한 특성의 소자를 제조할 수 있다.