• Journal of the Korean Crystal Growth and Crystal Technology
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• v.23 no.3
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• pp.119-123
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• 2013

Most of the world's solar cells in photovoltaic industry are currently fabricated using crystalline silicon. Czochralski-grown silicon crystals are more expensive than multicrystalline silicon crystals. The future of solar-grade Czochralski-grown silicon crystals crucially depends on whether it is usable for the mass-production of high-efficiency solar cells or not. It is generally believed that the main obstacle for making solar-grade Czochralski-grown silicon crystals a perfect high-efficiency solar cell material is presently light-induced degradation problem. In this work, the substitution of boron with gallium in p-type silicon single crystal is studied as an alternative to reduce the extent of lifetime degradation. The diamond-wire sawing technology is employed to slice the silicon ingot. In this paper, the quality of the diamond wire-sawn gallium-doped silicon wafers is studied from the chemical, electrical and structural points of view. It is found that the characteristic of gallium-doped silicon wafers including texturing behavior and surface metallic impurities are same as that of conventional boron-doped Czochralski crystals.

• Transactions on Electrical and Electronic Materials
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• v.16 no.2
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• pp.103-105
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• 2015

Effect of silicon doping into ZnSnO systems was investigated using solution process. Addition of silicon was used to suppress oxygen vacancy generation. The transfer characteristics of the device showed threshold voltage shift toward the positive direction with increasing Si content due to the high binding energy of silicon atoms with oxygen. As a result, the carrier concentration was decreased with increasing Si content.

• Journal of Convergence for Information Technology
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• v.12 no.4
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• pp.338-344
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• 2022

It is necessarily required in developing Si-based anode materials for lithium ion batteries, and the related researches are actively working especially in Si-carbon composite material. On the other hand, the photovoltaic and semiconductor industries discard huge amount of Si resources, facing the environmental issue. In this study, recycled Si resource is adopted to obtain Si-carbon composite for LIB(Lithium-Ion Batteries). In order to improve high-capacity retention characteristics and cycle stability of a Si anode material for the LIB, two differenct composites having a mass ratio of silicon and pitch of 1:1 and 2:1 are synthesized and electrochemical characteristics of the anode material manufactured by simple self-assembly method. This result in excellent initial capacity with stable cycle life, and confirming the potential use of recycled Si material for LIB.

• Korean Chemical Engineering Research
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• v.56 no.3
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• pp.320-326
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• 2018

In this study, Graphite/Silicon/Carbon (G/Si/C) composites were synthesized to improve the electrochemical properties of Graphite as an anode material of lithium ion battery. The prepared G/Si/C composites were analyzed by XRD, TGA and SEM. Also the electrochemical performances of G/Si/C composites as the anode were performed by constant current charge/discharge, rate performance, cyclic voltammetry and impedance tests in the electrolyte of $LiPF_6$ dissolved inorganic solvents (EC:DMC:EMC=1:1:1 vol%). Lithium ion battery using G/Si/C electrode showed better characteristics than graphite electrode. It was confirmed that as the silicon content increased, the capacity increased but the capacity retention ratio decreased. Also, it was shown that both the capacity and the rate performances were improved when using the Silicon (${\leq}25{\mu}m$). It is found that in the case of 10 wt% of Silicon (${\leq}25{\mu}m$), G/Si/C composites have the initial discharge capacity of 495 mAh/g, the capacity retention ratio of 89% and the retention rate capability of 80% in 2 C/0.1 C.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.440-440
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• 2009

Semiconductor nanowires offer exciting possibilities as components of solar cells and have already found applications as active elements in organic, dye-sensitized, quantum-dot sensitized, liquid-junction, and inorganic solid-state devices. Among many semiconductors, silicon is by far the dominant material used for worldwide photovoltaic energy conversion and solar cell manufacture. For silicon wire to be used for solar device, well aligned wire arrays need to be fabricated vertically or horizontally. Macroscopic silicon wire arrays suitable for photovoltaic applications have been commonly grown by the vapor-liquid-solid (VLS) process using metal catalysts such as Au, Ni, Pt, Cu. In the case, the impurity issues inside wire originated from metal catalyst are inevitable, leading to lowering the efficiency of solar cell. To escape from the problem, the wires of purity of wafer are the best for high efficiency of photovoltaic device. The fabrication of wire arrays by the electrochemical etching of silicon wafer with photolithography can solve the contamination of metal catalyst. In this presentation, we introduce silicon wire arrays by electrochemical etching method and then fabrication methods of radial p-n junction wire array solar cell and the various merits compared with conventional silicon solar cells.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.21-30
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• 2018

Driven by the recent energy saving trend, conventional silicon based power conversion modules are being replaced by modules using silicon carbide. Previous papers have focused mainly on the electrical advantages of silicon carbide semiconductors that can be used to design switching devices with much lower losses than conventional silicon based devices. However, no systematic study of their thermomechanical reliability in power conversion modules using finite element method (FEM) simulation has been presented. In this paper, silicon and silicon carbide based power devices with three-phase switching were designed and compared from the viewpoint of thermomechanical reliability. The switching loss of power conversion module was measured by the switching loss evaluation system and measured switching loss data was used for the thermal FEM simulation. Temperature and stress/strain distributions were analyzed. Finally, a thermal fatigue simulation was conducted to analyze the creep phenomenon of the joining materials. It was shown that at the working frequency of 20 kHz, the maximum temperature and stress of the power conversion module with SiC chips were reduced by 56% and 47%, respectively, compared with Si chips. In addition, the creep equivalent strain of joining material in SiC chip was reduced by 53% after thermal cycle, compared with the joining material in Si chip.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.15 no.2
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• pp.45-50
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• 2005

During oxidation process, several type of defects are formed on the surface of the silicon crystal which was damaged mechanically before oxidation. As the size of abrasive particle increases multiple dislocation loops are produced favorably over oxidation-induced stacking faults, which are dominantly produced when ground with finer abrasive particle. These defects are not related with the crystal growth process like Czochralski or directional solidification. During directional solidification process, twins and stacking faults are the two major defects observed in the bulk of the silicon crystal. On the other hand, slip dislocations produced by the thermal stress are not observed. Thus, not only in single crystalline silicon crystal but also in multi-crystalline silicon, extrinsic gettering process with programmed production of surface defects might be highly applicable to silicon wafers for purification.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.12
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• pp.1009-1014
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• 2012

Hydrogenated amorphous silicon (${\alpha}$-Si:H) layers deposited by plasma enhanced chemical vapor deposition (PECVD) are investigated for use in silicon hetero-junction solar cells employing n-type crystalline silicon (c-Si) substrates. The optical and structural properties of silicon hetero-junction devices have been characterized using spectroscopy ellipsometry and high resolution cross-sectional transmission electron micrograph (HRTEM). In addition, the effective carrier lifetime is measured by the quasi-steady-state photocoductance (QSSPC) method. We have studied on the correlation between the order of ${\alpha}$-Si:H and the passivation quality at the interface of ${\alpha}$-Si:H/c-Si. Base on the result, we have fabricated a silicon hetero-junction solar cell incorporating the ${\alpha}$-Si:H passivation layer with on open circuit voltage ($V_{oc}$) of 637 mV.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.413-413
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• 2009

Silicon nanowires (Si NWs)-based top-gate field-effect transistors (FETs) are constructed by using Si NWs transferred onto flexible plastic substrates. Si NWs are obtained from the silicon wafers using photolithography and anisotropic etching process, and transferred onto flexible plastic substrates. To evaluate the electrical performance of the silicon nanowires, we examined the output and transfer characteristics of a top-gate field-effect transistor with a channel composed of a silicon nanowire selected from the nanowires on the plastic substrate. From these FETs, a field-effect mobility and transconductance are evaluated to be $47\;cm^2/Vs$ and 272 nS, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.43-46
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.