• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.371-371
• /
• 2010

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the MEMS implementation with nano structure. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41{\AA}$, which have the gate area $10^{-3}cm^2$. The stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.119-119
• /
• 2008

The electrical characteristics of Metal-Ferroelectric-Nitride-Oxide-Silicon (MFNOS) structure is studied and compared to the conventional Silicon-Oixde-Nitride-Oxide-Silicon (SONOS) capacitor. The ferroelectric blocking layer is SrBiNbO (SBN with Sr/Bi ratio 1-x/2+x) with the thickness of 200 nm and is fabricated by the RF sputter. The memory windows of MFNOS and SONOS capacitors with sweep voltage from +10 V to -10 V are 6.9 V and 5.9 V, respectively. The effect of ferroelectric blocking layer and charge trapping on the memory window was discussed. The retention of MFNOS capacitor also shows the 10-years and longer retention time than that of the SONOS capacitor. The better retention properties of the MFNOS capacitor may be attributed to the charge holding effect by the polarization of ferroelectric layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.07a
• /
• pp.428-431
• /
• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11b
• /
• pp.201-204
• /
• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values, So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of $I_D-V_D$ $I_D-V_G$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.05a
• /
• pp.103-106
• /
• 1999

In this paper, we suggest the FED packaging technology that have 4mm thickness, using sodalime glass-to-sodalime glass electrostatic bonding. It based on conventional silicon-glass bonding. The silicon film was deposited an around the exhausting hole on FED backside panel. And then, the silicon film of panel was successfully bonded with capping(bare) glass in vacuum environment and the FED panel was vacuum-sealed. In this method, we could achieve more 153 times increased conductance and 200 times increased vacuum efficiency than conventional tube packaging method. The vacuum level in panel, by SRG test, was maintained about low 10$_{-4}$ Torr during above two months And, the light emission was observed to 0.7-inch tubeless packaged FED. Then anode current was 34 $\mu$ A. Emission stability was constantly measured for 10 days.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.2
• /
• pp.95-100
• /
• 2000

For the well-controlled growing in-situ heavily phosphorus doped polycrystalline Si films directly on Si wafer by reduced pressure chemical vapor deposition, a study is made of the two step growth. When in-situ heavily phosphorus doped Si films were deposited directly on Si (100) wafer, crystal structure in the film is not unique, that is, the single crystal to polycrystalline phase transition occurs at a certain thickness. However, the well-controlled polycrtstalline Si films deposited by two step growth grew directly on Si wafers. Moreover, the two step growth, which employs crystallization of grew directly on Si wafers. Moreover, the two step growth which employs crystallization of amorphous silicon layer grown at low temperature, reveals crucial advantages in manipulating polycrystal structures of in-situ phosphorous doped silicon.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11a
• /
• pp.201-204
• /
• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values. So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of I$_{D}$-V$_{D}$, I$_{D}$-V$_{G}$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.ristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.4
• /
• pp.255-260
• /
• 1998

Behavior of solid phase crystallizations (SPC) of RF sputtered and LPCVD amorphous hydrogenated silicon film were investigated. LPCVD films showed the higher degree of crystallinity and larger grain size than sputtered films. The applicable degree of crystallinity was also obtained from sputtered films. The deposition method of amorphous silicon film influenced the behavior of post annealing SPC. Observed degree of crystallinity of sputtered films strongly depended on the partial pressure of hydrogen in deposition. The higher deposition temperature of sputtering provided the better crystallinity after SPC. Due to the high degree of poly-crystallinity, the retardation of larger grain growth was observed on sputtering film.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.07a
• /
• pp.561-564
• /
• 2000

Silicon capacitive pressure sensor has been fabricated by using electrochemical etching stop and silicon-to-glass electrostatic bonding technique. A diaphragm structure is designed to compensate the nonlinear response. A cavity is etched into the silicon to the depth of 2$\mu\textrm{m}$ by anisotropic etching in 20wt.% TMAH solution at 80$^{\circ}C$. A fabricated sensor showed 3.3 pF zero-pressure capacitance, 297 pp.m/mmHg sensitivity, and a 7.4 7%F.S. nonlinear response in a 0-1 kgf/cm$^2$pressure range.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.152-153
• /
• 2006

본 연구에서는 태양전지 표면에 입사된 광자의 반사손실을 최소화하기 위한 방법으로써 기판 표면에 다공성 실리콘층을 이용한 반사방지막 (Anti-Reflection Coating, ARC)을 형성하는 실험을 하였다. 다공성 실리콘(Porous silicon, PSi)은 실온에서 일정 비율로 만든 전해질 용액($HF-C_2H_5OH-H_2O$)을 사용하여 실리콘 표면을 양극산화처리 함으로써 단순 공정만으로 실리콘 기판의 반사율을 높일 수 있다. 또한 새로운 레이어(layer)없이 기존 기판을 식각시켜 만들기 때문에 박막형 태양전지를 제작시 적용이 용이하다. 저비용, 단순공정의 이점을 살려 전류밀도에 따른 PSi의 반사방지막으로써의 특성을 비교 분석하였다.