• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.28B no.5
• /
• pp.318-326
• /
• 1991

A Quantizer reconstruction level control method for block artifact reduction in DCT image coding is described. In our scheme, quantizer reconstruction level control is obtained by adding quantization level step size to the optimum quantization level in the direction of reducing the block artifact by minimizing the mean square error(MSE) and error difference(EDF) distribution in boundary without the other additional bits. In simulation results, although the performance in terms of signal to noise ratio is degraded by a little amount, mean square of error difference at block boundary and mean square error having relation block artifact is greatly reduced. Subjective image qualities are improved compared with other block artifact reduction method such as postprocessing by filtering and trasform coding by block overlapping. But the addition calculations of 1-dimensional DCT become to be more necessary to coding process for determining the reconstruction level.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.39 no.1
• /
• pp.76-83
• /
• 2011

This paper focuses on the thermal design of a signal processor in Micro-Wave Seeker. High temperature environment and ESS(Environmental Stress Screening) test condition should be considered in designing a signal processor. First, we performed the thermal analysis to know conditions under which a signal processor is thermally reliable. As a result of thermal analysis, we found that adopting heat transfer block to the thermally fragile components is most efficient, because the heat transfer block can control the thermal loads of the individual components. Next, we verified this solution by numerical simulation and experiment and concluded that thermal reliability of a signal processor can be achieved. Maximum temperature difference between numerical simulation and experiment is about $2^{\circ}C$.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.53-56
• /
• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.5
• /
• pp.849-855
• /
• 1987

This paper describes an implementation of the absolute moment block truncation coding(AMBTC) in real time for the moving picture data compression. We have realized a system composed of the encoder and decoder, and operated it using an NTSC TV signal. The encoder consists of a 4-1line buffer memory and a data processing block. Besides, there are signal conditioner and a control signal generator. Experimental results show that the quality of the processed image with a data rate of 10Mb/s is slightly degraded, but not objectionable, comparing data rate of 80Mb/s.

• Journal of the Korea institute for structural maintenance and inspection
• /
• v.4 no.2
• /
• pp.167-174
• /
• 2000

Ground penetrating radar(GPR) was applied for measuring depths, sizes and intervals of rebars embedded in concrete. A concrete wall was constructed for this study and a sand pool and a concrete block were used for simulation. Result of this study shows that GPR can be used for measuring rebar depths and intervals, even though it is limitary, but that measuring sizes is almost impossible. Simulation with the sand pool was helpful for research on the versatile rebar arrays though signal was not clear as real concrete wall. A concrete block with many cylindrical holes for inserting different sized rebars could not be used for simulator due to many unknown reflective waves. Antenna orientation must be perpendicular to rebars for large reflection signal.

• Journal of Positioning, Navigation, and Timing
• /
• v.12 no.1
• /
• pp.59-65
• /
• 2023

A GNSS receiver must perform signal acquisition to estimate the code phase and Doppler frequency of the incoming satellite signals, which are essential information for baseband signal processing. Modernized GNSS signals have different modulation schemes and long PRN code lengths from legacy signals, which makes it difficult to acquire the signals and increases the computational complexity and time. This paper proposes a novel FFT/Inverse-FFT with baseband resampling to resolve the aforementioned challenges. The suggested algorithm uses a single block only for the FFT and thereby requires less hardware resources than conventional structures such as Double Block Zero Padding (DBZP). Experimental results based on a MATLAB simulation show this algorithm can successfully acquire GPS L1C/A, GPS L2C, Galileo E1OS, and GPS L5.

• Journal of information and communication convergence engineering
• /
• v.1 no.3
• /
• pp.119-122
• /
• 2003

In this paper presents equations which describe an average weighted spectrum of errors and average block error probabilities for noncoherent frequency shift keying (NCFSK) used in D-branch maximal ratio combining (MRC) diversity in independent very slow nonselective Nakagami fading channels. The average is formed over the instantaneous receiver signal to noise ratio (SNR) after combining. the analysis is limited to additive Gaussian noise.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.11C
• /
• pp.880-882
• /
• 2008

This paper presents LDPC codes' upper bounds over the waterfall SNR region. The previous researches have focused on the average bound or ensemble bound over the whole SNR region and showed the performance differences for the fixed block size. In this paper, the particular LDPC codes' upper bounds for various block sizes are calculated over the waterfall SNR region and are compared with BP decoding performance. For different block sizes the performance degradation of BP decoding is shown.

• Journal of the Institute of Convergence Signal Processing
• /
• v.9 no.1
• /
• pp.46-53
• /
• 2008

This paper presents a 13.56 MHz RFID reader that can be used as a door-lock system for smart home security. The RFID reader consists of a transmitter, a receiver, and a data processing block. To verify the operation of the developed RFID reader, we present both a PSPICE simulation for transmitter/receiver and a digital simulation for data processing block. In particular, a CRC block for error detection of received data and a Manchester decoding block for position detection of collided data are designed using VHDL. In addition, we applied a binary search algorithm for multi-tag anti-collision. The anti-collision procedure is carried out by PIC microcontroller on software. The experimental results show that the developed reader can provide the right multi-tag recognition.

• 제어로봇시스템학회:학술대회논문집
• /
• 1997.10a
• /
• pp.163-166
• /
• 1997

In order to shorten head-way time on existing railway lines without any change of signal block length between stations, it is a realistic optional way to change the control method of train signal, i.e. to modernize the cab signal using transponder. A new signalling system of operation pattern control technique is suggested as new model to increase the railway traffic efficiency. Through the computer simulation of this model, the train head-way time by the fixed signalling system and the new pattern control system is analyzed.