• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.5
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• pp.71-77
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• 2020

Recently, the tracking radar has confirmed the necessity of developing a small tracking radar that can be operated without various restrictions in various environments. In addition, the performance of a small tracking radar requires equal to or higher than the existing tracking radar. Such a small tracking radar can be implemented through miniaturization and low power of existing tracking radar. In this paper, the role and function of a signal processor for a small tracking radar are defined and we proposed a method to increase the efficiency of power consumption and miniaturization by minimizing the use of devices required to implement a signal processor for a small tracking radar. Used as a method for miniaturization, a device processor such as DDC and communication controller was implemented in an FPGA to design a signal processor for a small tracking radar. In addition, a low-power signal processor was designed by a power supply using a highly efficient switching regulator. Finally, the signal processor was verified by the performance test of the signal processor for the small tracking radar implemented, the Doppler tracking test using the signal processor on the small tracking radar, and the distance tracking test.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.134-141
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• 2019

Radar systems are divided into the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar depending on the transmission waveform. In particular, the PD radar is advantageous for long-range target detection, and the FMCW radar is suitable for short-range target detection. In this paper, we present design and implementation results for a multi-mode radar signal processor (RSP) that can support both PD and FMCW radar systems to detect unmanned aerial vehicles (UAVs) at short distances as well as long distances. The proposed radar signal processor can be implemented based on Altera Cyclone-IV FPGA with 19,623 logic elements, 9,759 registers, and 25,190,400 memory bits. The logic elements and registers of the proposed radar signal processor are reduced by approximately 43% and 30%, respectively, compared to the sum of logic elements and registers of the conventional PD radar and FMCW radar signal processor.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1241-1245
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• 2009

As FFT(Fast Fourier Transform) processor is used in OFDM(Orthogonal Frequency Division Multiplesing) system. According to increase requirement about mobility and broadband, Research about low power and low area FFT processor is needed. So research concern in reduction of memory size and complex multiplier is in progress. Increasing points of FFT increase memory area of FFT processor. Specially, SRU(Signal Reordering Unit) has the most memory in FFT processor. In this paper, we propose a reduced method of memory size of SRU in FFT processor. SRU of 64, 1024 point FFT processor performed implementation by VerilogHDL coding and it verified by simulation. We select the APEX20KE family EP20k1000EPC672-3 device of Altera Corps. SRU implementation is performed by synthesis of Quartus Tool. The bits of data size decide by 24bits that is 12bits from real, imaginary number respectively. It is shown that, the proposed SRU of 64point and 1024point achieve more than 28%, 24% area reduction respectively.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.1
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• pp.140-146
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• 2010

The multi-function radar can detect and track the low RCS targets. For this purpose the multi-function radar uses the pulse train waveform. because this waveform has high dynamic range and good SNR(Signal to Noise Ratio). But the spurious signals can also be detected by processing the pulse train waveform. Thus the multi-function radar signal processor must have the high SFDR(Spurious Free Dynamic Range). This paper describes the development of the multi-function radar signal processor having the high SFDR.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.1
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• pp.119-127
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• 2012

This paper describes development and performance test of signal processor for the millimeter wave seeker. A ground to air guidance missile is required various beam patterns in order to counteract different kind of target. Therefore, we designed the hardware and software architecture considering flexibility. This signal processor consists of ADC, FPGA, DSP and etc. FPGA provides peripheral interface to DSP and convert digital IF signal to baseband signal. DSP performs signal processing, calculates target's information and controls devices. Each parts' hardware are connected in series and signal processing algorithms for various beam patterns are built in parallel.

• Journal of Biomedical Engineering Research
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• v.15 no.3
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• pp.281-288
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• 1994

In this paper, a new decomposition method of the interference EMG signal using MAMDF filtering and digital signal processor. The efficient software and hardware signal processing techniques are employed. The MAMDF filter is employed in order to estimate the presence and likely location of the respective templates which may include in the observed mixture, and high-resolution waveform alignment is employed in order to provide the optimal combination set and time delays of the selected templates. The TMS320C25 digital signal processor chip is employed in order to execute the intensive calculation part of the software. The method is verified through a simulation with real templates which are obtain ed from needle EMG. As a result, the proposed method provides an overall speed improvement of 32-40 times.

• Korean Journal of Remote Sensing
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• v.21 no.6
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• pp.483-491
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• 2005

SAR signal processing technique has been considered a crucial technical part in order to generate an image from radar signal data and ADD (Agency for Defense Development) has focused on this area for years to develope our own SAR Processor for various SAR systems (Radarsat, ERS, KOMSAR). In this paper, we investigated major techniques related to generation of SAR images and developed ASPR (ADD SAR Processor for Radarsat) practically using the commercial Radarsat-1 radar signal data (RAW). We demonstrated the performance of the ASPR in comparison with the image generated by MDA and Vexcel's SAR Processor (FOCUS).

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.15 no.8 s.101
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• pp.954-961
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• 2005

This paper is concerned with the implementation of auto-tuning positive position feedback controller using a digital signal processor and microcontroller. The main advantage of the positive position feedback controller is that it can control a natural mode of interest by tuning the filter frequency of the positive position feedback controller to the natural frequency of the target mode. However, the positive position feedback controller loses its advantage when mistuned. In this paper, the fast fourier transform algorithm is implemented on the microcontroller whereas the positive position feedback controller is implemented on the digital signal processor. After calculating the frequency which affects the vibrations of structure most, the result is transferred to the digital signal processor. The digital signal processor updates the information on the frequency to be controlled so that it can cope with both internal and external changes. The proposed scheme was installed and tested using a beam equipped with piezoceramic sensor and actuator. The experimental results show that the auto-tuning positive position feedback controller proposed in this paper can suppress vibrations even when the target structure undergoes structural change thus validating the approach.