• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.2
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• pp.193-199
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• 2009

In this paper, impedance analysis of a differential pall having 2 drop configuration is performed using the reflection theory and verified by circuit simulator (Ansoft designer). Through the impedance analysis, it was possible to understand the signal transmission at a differential pall, and an optimized 2 drop design technique of a differential pair could be developed. When compared with the conventional design, the proposed design shows a good signal integrity and has much less design restrictions.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.366-375
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• 2008

Generally a return current plane(RCP) of high speed digital and analog part is partitioned. This is achieved in order to decrease the noise interference between subsystem in PCBs(Printed Circuit Boards). However, when the connected signal line exists between each sub system, this partition will cause unwanted effects. In a circuital point of view, RCP partition has a bad influence upon signal integrity. In a EMI(Electromagnetic Interference) point of view, the partition of the return current plane becomes a primary factor to increase the radiated emission. Component bridge(CB) is usecl for the way of maintaining signal integrity, still specific user's guide doesn't give sufficient principle. In a view point of signal integrity, design principle of multi-CB using method will be analyzed by measurement and simulation. And design principle of noise mitigation will be provided. Generally interval of CB is ${\lambda}/20$ ferrite bead. In this study. When multi-CB connection is applied, design principle of ferrite bead and chip resistor is proved by measurement and simulation. Multi-connected chip resistance$(0{\Omega})$ is proved to be more effective design method in the point of signal integrity.

• Proceedings of the Korean Reliability Society Conference
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• 2004.07a
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• pp.37-72
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• 2004

Future Circuit Design means "Unimaginable Intricate Engineering Problems" Thus, Future Circuit Designers may be "Victims" of "Inexorably Complicated Signal Integrity Problems".(omitted)grity Problems".(omitted)tted)

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

• Journal of electromagnetic engineering and science
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• v.5 no.4
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• pp.193-196
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• 2005

The DC power-bus for the PCB is loaded with metal walls on its selected sides and is characterized electromagnetically. This is a novel concept of approach to mitigate the spurious resonance and finally signal integrity problems. In particular, the peak at DC, which is always in the way to secure parallel-plates' EMC, can be completely removed by the proposed method. Through the findings of this study, the effect of metal-loading of the power-bus will be presented along with the impression that the suggested technique can tackle the headaches of signal integrity, ground bounce, EMIs.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.175-183
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• 2016

This paper brings out a novel method for reducing Near end and Far end Crosstalk using Electromagnetic Band Gap structures (EBG) in High Speed RF transmission lines. This work becomes useful in high speed closely spaced Printed Circuit Board (PCB) traces connected to multi core processors. By using this method, reduction of −40dB in Near-End Crosstalk (NEXT) and −60 dB in Far End Crosstalk (FEXT) is achieved. The results are validated through experimental measurements. Time domain analysis is performed to validate the signal integrity property of coupled transmission lines.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.491-492
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• 2008

According to high-speed large scale integration trend of Memory module product, many type of noises, such a reflection, cross-talk simultaneous switching noise, occur on the Package PCB and they make the deterioration of memory module's performance and reliability. As module products have more high efficiency, Hardware of test board and socket has to be considered In test of the high-speed Memory Module. we mainly focused on improvement of Signal integrity Using the High Frequency Test socket that we invented

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.15-22
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• 2011

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

• Journal of Advanced Navigation Technology
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• v.21 no.1
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• pp.58-65
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• 2017

Global navigation satellite system (GNSS) has a weakness of signal integrity caused by broadcasting type data transmitting direct to user from navigation satellite. Loss of GNSS signal integrity can make a catastrophic event in the operation of unmanned aerial system (UAS) because position decision is only depended on GNSS. So it is required to apply alternative method to reduce a risk and to guarantee a GNSS signal integrity for UAS operation. This paper addressed the reason of loosing GNSS signal integrity, the effectiveness of signal jamming/spoofing and GNSS application trend for UAS. Also suggested the flight safety enhancing method in case of GNSS signal jamming for UAS as technical and political approaches.

• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.3
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• pp.248-251
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• 2014

As more vehicles become equipped with advanced electronic control systems, more consideration is needed with regards to automotive safety issues related to the effects of electromagnetic waves. Unwanted electromagnetic waves from the antenna, electricity and other electronic devices cause the performance and safety problem of automotive components. In general, Power Integrity and Signal Integrity analysis have been widely used, but these analyses have stayed PCB level. PCB base analysis is different from radiated emission TEST condition so its results are used just for reference. This paper proposes EMC optimization technology using module level 3-dimensional radiation simulation process closed to fundamental test conditions. If module level EMC analysis, which is proposed in this study, is applied to all automotive electronics systems, unexpected EMC noise will be prevented.