• Title/Summary/Keyword: Signal Demodulator

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Simultaneous Measurement of Strain and Damage Signal of Composite Structures Using a Fiber Bragg Grating Sensor (광섬유 브래그 격자 센서를 이용한 복합재 구조물의 변형률 및 파손신호 동시 측정)

  • Koh Jong-In;Bang Hyung-Joon;Kim Chun-Gon;Hong Chang-Sun
    • Proceedings of the Korean Society For Composite Materials Conference
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    • 2004.04a
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    • pp.95-102
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    • 2004
  • For the simultaneous measurement of strain and damage signal, a fiber Bragg grating sensor system with a dual demodulator was proposed. One demodulator using a tunable Fabry-Perot filter can measure low-frequency signal such as strain and the other demodulator using a passive Mach-Zehnder interferometer can detect high-frequency signal such as damage signal or impact signal. Using a proposed fiber Bragg grating sensor system, both the strain and damage signal of a cross-ply laminated composite beam under tensile loading were simultaneously measured. Analysis of the strain and damage signals detected by single fiber Bragg grating sensor showed that sudden strain shifts were induced due to transverse crack propagation in the 90 degree layer of composite beam and vibration with a maximum frequency of several hundreds of kilohertz was generated.

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A New Carrier Recovery Algorithm Usign $\theta$-matching method for QAM Demodulator ($\theta$-정합을 이용한 QAM 복조용 Carrier Recovery)

  • 박휘원;장일순정차근조경록
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.179-182
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    • 1998
  • Carrier recovery, the process of recoverying the carrier in receiver, removes the phase difference between VCO and the received signal. However, the conventional structure of carrier recovery cannot be applied to multi-level QAM demodulator because of the increasing decision interval and the complexity of control as the number of symbol increases. In this paper, we suggest a new carrier recovery algorithm using $\theta-matching$ algorithm for multi-level QAM demodulation to overcome this problem and analysis the performance and implement it.

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A DPSK Demodulator of Direct Sequence Spread Spectrum using SAW Convolver (탄성표면파 콘벌버를 이용한 직접 시퀀스 대역 확산 통신에서의 DPSK 복조에 관한 연구)

  • Lee, Dong-Wook;Cho, Kwan;Whang, Keum-Chan
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.15 no.6
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    • pp.494-505
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    • 1990
  • This paper reports on the development of a DPSK demodulator of DS spread spectrum communications that use one SAW convolver. The spreading code chip pattern is changed from bit to bit in data portion of packet. And code chip is PSK modulated. Compared with simulation, experiment shows that the DPSK signal spreaded can be demodulated by using only one SAW convolver. And the theoretical performance of this DPSK demudulator is equal to CSK demodulator wich uses two SAW convolvers.

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Design and Implementation of phase sensitive RF Modulator/Demodulator using Amplitude Modulation (진폭변조방식을 이용한 Phase Sensitive RF Modulator/Demodulator의 설계 및 제작)

  • Kim, Jun-Woo;Chung, Jae-Ho;Mun, Chi-Woong;Oh, Chang-Hyun;Yi, Yun
    • Proceedings of the KOSOMBE Conference
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    • v.1995 no.05
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    • pp.167-170
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    • 1995
  • A quadrature-channel MODEM using amplitude modulation was constructed. To test the MODEM, 6.4 MHz sinusoidal wave 1 KHz triangular wave were modulated, then the modulated signal was fed into the demodulator, to reconstruct the triangular wave.

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A Study about Performance Improvement of Return Link Demodulator for Satellite Communication (위성 통신용 리턴 링크 복조기의 성능 개선에 관한 연구)

  • Wang, Do-Huy;Oh, Deock-Gil
    • Journal of Satellite, Information and Communications
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    • v.7 no.1
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    • pp.92-96
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    • 2012
  • This paper presents return link demodulation algorithm designed for hardware implementation using HDL that include complex signal processing work reliably even in low SNR. Simulation results show that performance of Es/$N_0$ has improved within 0.5dB at the point of uncoded BER $10^{-3}$ compared to the ideal QPSK signal. In addition, fixed-point simulation and HDL implementation performance compared to the simulation we can see that there is no difference.

A 13.56 MHz Radio Frequency Identification Transponder Analog Front End Using a Dynamically Enabled Digital Phase Locked Loop

  • Choi, Moon-Ho;Yang, Byung-Do;Kim, Nam-Soo;Kim, Yeong-Seuk;Lee, Soo-Joo;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.1
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    • pp.20-23
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    • 2010
  • The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

Implementation of Real-time Stereo Frequency Demodulator Using RTL-SDR (RTL-SDR을 이용한 스테레오 주파수 변조 방송의 실시간 수신기 구현)

  • Kim, Young-Ju
    • Journal of Broadcast Engineering
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    • v.24 no.3
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    • pp.485-494
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    • 2019
  • A software-driven real-time frequency de-modulator is implemented with the aid of universal-serial-bus (USB) type software defined radio dongle. An analog stereo frequency modulation (FM) broadcast signal is down-converted to the basedband analog signal then converted to digital bit streams in the USB dongle. Computer software such as Matlab, Python, and GNU Radio manipulates the incoming bit streams with the technique of digital signal processing. Low pass filtering, band pass filtering, decimation, frequency discriminator, double sideband amplitude demodulation, phase locked loop, and deemphasis function blocks are implemented using such computer languages. Especially, GNU Radion is employed to realize the real-time demodulator.

Design and Implementation of 64 QAM(155Mbps) Demodulator for Transmitting Digital Microwave Radio (Digital Microwave Radio 신호전송을 위한 64QAM(155Mbps) 복조기 설계 및 구현)

  • 방효창;안준배;이대영;조성준;김원후
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.11
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    • pp.2081-2093
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    • 1994
  • In this study, we design and implement 64 QAM demodulator which has 155 Mbps, first level of CCITT G707 SDH(Synchronous Digital Hierachy) for STM 1 signal transmission. Carrier recovery which effects the demodulator performance uses decision feedback carrier using 8 bits A/D converter. Also, PSF(Pulse Shaping Filter) is 7 order elliptic filter. Carrier recovery circuit is designed and implemented digital type which use high 3 bits of 8 bits conversion data as data and the order low bits as error data and hybrid type which use VCO and analog integrator. Therefore we obtain stable performance recovery.

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A 4.8-Gb/s QPSK Demodulator For 60-GHz WPAN (60GHz 대역 WPAN을 위한 4.8Gb/s QPSK 복조기)

  • Kim, Du-Ho;Choi, Woo-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.1
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    • pp.7-13
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    • 2011
  • A mixed-mode QPSK demodulator for 60-GHz wireless personal area network application is demonstrated. In this work, mixed-mode QPKS demodulation scheme achieving low power consumption and small area is employed. The prototype chip realized by 60-nm CMOS Logic process can demodulate up to 4.8-Gb/s QPSK signals at 4.8-GHz carrier frequency. At this carrier frequency, the demodulator core consumes 54 mW from 1.2-V power supply while the chip area is $150{\times}150{\mu}m^2$. Using the fabricated chip, transmission and demodulation of 1.7-GSymbol/s QPSK signal in 60-GHz link is demonstrated.

Performance Analysis of Access Channel Decoder Implemeted for CDMA2000 1X Smart Antenna Base Station (CDMA2000 1X 스마트 안테나 기지국용으로 구현된 액세스 채널 복조기의 성능 분석)

  • 김성도;현승헌;최승원
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.2A
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    • pp.147-156
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    • 2004
  • This paper presents an implementation and performance analysis of an access channel decoder which exploits a diversity gain due to the independent magnitude of received signals energy at each of antenna elements of a smart antenna BTS (Base-station Transceiver Subsystem) operating in CDMA2000 1X signal environment. Proposed access channel decoder consists of a searcher supporting 4 fingers, Walsh demodulator, and demodulator controller. They have been implemented with 5 of 1 million-gate FPGA's (Field Programmable Gate Array) Altera's APEX EP20K1000EBC652 and TMS320C6203 DSP (digital signal processing). The objective of the proposed access channel decoders is to enhance the data retrieval at co]1-site during the access period, for which the optimal weight vector of the smart antenna BTS is not available. Through experimental tests, we confirmed that the proposed access channel decoder exploitng the diversity technique outperforms the conventional one, which is based on a single antenna channel, in terms of detection probability of access probe, access channel failure probability, and $E_{b/}$ $N_{o}$ in Walsh demodulator.r.r.