• Journal of the Korean Geotechnical Society
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• v.35 no.5
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• pp.21-30
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• 2019

While the study of the shallow tunnel has been mainly on the longitudinal load transfer and horizontal surface conditions, the study of the ground behavior of shallow tunnel under the slope is not sufficient. Therefore, in this study on the ground behavior around a tunnel due to the sidewall deformation of shallow tunnel under the slope that is excavated in longitudinal direction, a scale-down model test has been performed. The model tunnel has the dimension of 320 mm wide, 210 mm high and 55 mm long with enough material strength in aluminum and the model ground has the uniform ground conditions by 3 types of carbon rods. The model test has been performed with the variables of slopes and the cover depths by controlling the tunnel sidewall deformation, and the change of sidewall-load, load transfer, ground subsidence was monitored and analyzed. According to the increase of the slope, the maximum ground subsidence increased by 20~39% compared to the horizontal surface. The load ratio increased by maximum 20% in the tunnel crown and decreased in sidewall according to the surface slope. The load transfer shows maximum 128% of increase at the cover depth of 1.0D, while at the 1.5D cover depth it shows non-critical difference from horizontal surface. The slope has major effects on load transfer at the cover depth of 1.0D.

• Journal of Electrical Engineering and Technology
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• v.4 no.4
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• pp.546-551
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• 2009

In this paper, we describe a self-aligned fabrication method for a nano-patterned bottom electrode using flood exposure from the backside. Misalignments between layers could cause the final devices to fail after the fabrication of the nano-scale bottom electrodes. A self-alignment was exploited to embed the bottom electrode inside the glass substrate. Aluminum patterns act as a dry etching mask to fabricate glass trenches as well as a self-aligned photomask during the flood exposure from the backside. The patterned photoresist (PR) has a negative sidewall slope using the flood exposure. The sidewall slopes of the glass trench and the patterned PR were $54.00^{\circ}$ and $63.47^{\circ}$, respectively. The negative sidewall enables an embedment of a gold layer inside $0.7{\mu}m$ wide glass trenches. Gold residues on the trench edges were removed by the additional flood exposure with wet etching. The sidewall slopes of the patterned PR are related to the slopes of the glass trenches. Nano-scale bottom electrodes inside the glass trenches will be used in beam resonators operating at high resonant frequencies.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.21-28
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• 1999

A new method of making high speed self-aligned ESD (Elevated Source/Drain) MOSFET is proposed. Different from the conventional LDD (Lightly-Doped Drain) structure, the proposed ESD structure needs only one ion implantation step for the source/drain junctions, and makes it possible to modify the depth of the recessed channel by use of dry etching process. This structure alleviates hot-carrier stress by use of removable nitride sidewall spacers. Furthermore, the inverted sidewall spacers are used as a self-aligning mask to solve the self-align problem. Simulation results show that the impact ionization rate ($I_{SUB}/I_{D}$) is reduced and DIBL (Drain Induced Barrier Lowering) characteristics are improved by proper design of the structure parameters such as channel depth and sidewall spacer width. In addition, the use of removable nitride sidewall spacers also enhances hot-carrier characteristics by reducing the peak lateral electric field in the channel.

• Applied Chemistry for Engineering
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• v.20 no.1
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• pp.99-103
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• 2009

HBr and $O_2$ in $Cl_2$ gas ambient for the high density plasma gate etching has been used to increase the performance of gate electrode in semiconductor devices. When an un-doped amorphous silicon layer was used for a gate electrode material, the notching profile was observed at the outer sidewall foot of the outermost line. This phenomenon can be explained by the electron shading effect: i.e., electrons are captured at the photoresist sidewall while ions pass through the photoresist sidewall and reach the oxide surface at a narrowly spaced pattern during the over etch step. The potential distribution between gate lines deflects the ions trajectory toward the gate sidewall. In this study, an appropriate mechanism was proposed to explain the occurrence of notching in the gate electrode of un-doped amorphous silicon.

• Journal of Sensor Science and Technology
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• v.24 no.1
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• pp.10-14
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• 2015

This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.5
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• pp.151-156
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• 2020

To analyze the diffraction properties of optical signals and the significant impacts of tapered sidewall profile at periodic trapezoidal 2D diffraction gratings, Toeplitz dielectric tensor is first defined and formulated by 2D spatial Fourier expansions associated with trapezoidal profile. The characteristic modes in each layer is then based on eigenvalue problem, and the complete solution is found rigorously in terms of modal transmission-line theory (MTLT) to address the pertinent boundary-value problems. Based on those one, the numerical analysis is performed on how the tapered side profile of grating structures with trapezoidal refractive index distribution affects the design of a sub-wavelength grating reflector. The numerical results reveal that this tapered sidewall profile plays a critical role in determining the reflection bandwidth, the average reflectance, and the band edge.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.125.2-125.2
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• 2016

Semiconductor nanowires are essential building blocks for various nanotechnologies including energy conversion, optoelectronics, and thermoelectric devices. Bottom-up synthetic approach utilizing metal catalyst and vapor phase precursor molecules (i.e., vapor - liquid - solid (VLS) method) is widely employed to grow semiconductor nanowires. Al has received attention as growth catalyst since it is free from contamination issue of Si nanowire leading to the deterioration of electrical properties. Al-catalyzed Si nanowire growth, however, unlike Au-Si system, has relatively narrow window for stable growth, showing highly tapered sidewall structure at high temperature condition. Although surface chemistry is generally known for its role on the crystal growth, it is still unclear how surface adsorbates such as hydrogen atoms and the nanowire sidewall morphology interrelate in VLS growth. Here, we use real-time in situ infrared spectroscopy to confirm the presence of surface hydrogen atoms chemisorbed on Si nanowire sidewalls grown from Al catalyst and demonstrate they are necessary to prevent unwanted tapering of nanowire. We analyze the surface coverage of hydrogen atoms quantitatively via comparison of Si-H vibration modes measured during growth with those obtained from postgrowth measurement. Our findings suggest that the surface adsorbed hydrogen plays a critical role in preventing nanowire sidewall tapering and provide new insights for the role of surface chemistry in VLS growth.

• Proceedings of the Korea Concrete Institute Conference
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• 1999.10a
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• pp.329-332
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• 1999

The crack of concrete induced by the heat of hydration is a serious problem, particularly in concrete structures such as underground box structure, mat-slab of nuclear reactor buildings, dams or large footings, foundations of high rise buildings, etc.. As a result of the temperature rise and restriction condition of foundation, the thermal stress which may induce the cracks can occur. Therefore the various techniques of the thermal stress control in massive concrete have been widely used. One of them is prediction of the thermal stress, besides low-heat cement which mitigates the temperature rise, pre-cooling which lowers the initial temperature of fresh concrete with ice flake, pipe cooling which cools the temperature of concrete with flowing water, design change which considers steel bar reinforcement, operation control and so on. The objective of this paper is largely two folded. Firstly we introduce the cracks control technique by employing low-heat cement mix and thermal stress analysis. Secondly it show the application condition of the cracks control technique like sidewall of LNG in Inchonl.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.833-837
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• 2012

This paper proposes a DRAM data retention time enhancement method that minimizes silicon loss and undercut at STI sidewall by reducing the SC1 (Standard Cleaning) time. SC1 time optimization debilitates the parasitic electric field in STI's top corner, which reduces an inverse narrow width effect to result in reduction of channel doping density without increasing the subthreshold leakage of cell Tr. Moreover, it minimizes the electric field in depletion area from cell junction to P-well, increasing yield or data retention time.

• Proceedings of the KSME Conference
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• 2000.11a
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• pp.387-394
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• 2000

Theoretical and experimental study is conducted on the contact pressure distribution of a radial tire in motion under various camber angles. Tire construction is modelled by a spring bedded elastic ring, consisted of sidewall springs and a composite belt ring. The contact area is assumed to be a trapezoidal shape varying with camber angles and weighted load. The basic equation in a quasi-static form is derived for the deformation of a running belt with a constant velocity by the aid of Lagrange-Euler transformation. Galerkin's method and stepwise calculation are applied for solving the basic equation and the mechanical boundary condition along both sides of the contact belt part subjected to shearing forces transmitted from the sidewall spring. Experimental results on the contact pressure, measured by pressure sensors embedded in the surface of the drum tester, correspond well with the calculated ones for the test tire under various camber angles, running velocities and weighted loads. These results indicate that a buckling phenomenon of the contact belt in the widthwise direction occurs due to the effect of camber angle.